This paper presents a new bit-interleaving 12T subthreshold SRAM cell with Data-Aware Power-Cutoff (DAPC) Write-assist to improve the Write-ability to mitigate increased device variations at low supply voltage under deep sub-100 nm processes. The disturb-free feature facilitates the bit-interleaving architecture that can reduce multiple-bit errors in a single word and enhance soft error immunity by employing error checking and correction (ECC) techniques. The proposed 12T SRAM cell is demonstrated by a 4 kb SRAM macro implemented in 40 nm general purpose (40GP) CMOS technology. The test chip operates from typical VDD to 350 mV ( ~ 100 mV lower than the threshold voltage) with VDDMIN limited by Read operation. Data can be written successfully for VDD down to 300 mV. The measured maximum operation frequency is 11.5 MHz with total power consumption of 22 μW at 350 mV, 25 °
C.

https://ir.nctu.edu.tw:443/bitstream/11536/25204/1/000341593700007.pdf

40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist

Low power and noise tolerant static random access memory (SRAM) cells are in high demand today. This paper presents a stable differential SRAM cell that consumes low power. The proposed cell has similar structure to conventional 6T SRAM cell with the addition of two buffer transistors, one tail transistor and one complementary word line. Due to stacking effect, the proposed cell achieves lower power dissipation. In this paper, impact of process parameters variations on various design metrics of the proposed cell are presented and compared with conventional differential 6T (D6T), transmission gate-based 8T (TG8T), and single ended 8T (SE8T) SRAM cells. Impact of process variation, like threshold voltage and length, on different design metrics of an SRAM cell like, read static noise margin (RSNM), read access time ( ${T_{\mathrm{RA}}}$ ), and write access time ( ${T_{\mathrm{ WA}}} $ ) are also presented. The proposed cell achieves ${1.12{\times } /{\mathrm{ 1}}.{\mathrm{ 43}}{\times } /{\mathrm{ 5}}.{\mathrm{ 62}}\times } $ improvement in ${T_{\mathrm {RA}}}$ compared to TG8T/D6T/SE8T at a penalty of $ {1.1{\times } /{4}.{88}\times }$ in $ {T_{\mathrm{ WA}}} $ compared to D6T/TG8T and $ {1.19{\times } /1.18\times } $ in read/write power consumption compared to D6T. An improvement of $ {\rm 1.{\mathrm{ 12}}{\times } /{\mathrm{ 2}}.{\mathrm{ 15}}\times } $ in RSNM is observed compared to D6T/TG8T. The proposed cell consumes $ {5.38\times } $ less power during hold mode and also shows ${2.33\times } $ narrower spread in hold power @ $ {V_{\mathrm{ DD}} = 0.{\mathrm{ 4}}}$ V compared to D6T SRAM cell.

Variation Tolerant Differential 8T SRAM Cell for Ultralow Power Applications

This paper presents a 9T multi-threshold (MTCMOS) SRAM macro with equalized bitline leakage and a content-addressable-memory-assisted (CAM-assisted) write performance boosting technique for energy efficiency improvement. A 3T-based read port is proposed to equalize read bitline (RBL) leakage and to improve RBL sensing margin by eliminating data-dependence on bitline leakage current. A miniature CAM-assisted circuit is integrated to conceal the slow data development with HVT devices after data flipping in write operation and therefore enhance the write performance for energy efficiency. A 16 kb SRAM test chip is fabricated in 65 nm CMOS technology. The operating voltage of the test chip is scalable from 1.2 V down to 0.26 V with the read access time from 6 ns to 0.85 $\mu {\rm s}$ . Minimum energy of 2.07 pJ is achieved at 0.4 V with 40.3% improvement compared to the SRAM without the aid of the CAM. Energy efficiency is enhanced by 29.4% between 0.38 V $\sim$ 0.6 V by the proposed CAM-assisted circuit.

https://dr.ntu.edu.sg/bitstream/10220/39677/1/Design%20of%20an%20Ultra-low%20Voltage%209T%20SRAM%20with.pdf

Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement

Higher noise tolerance, lower power consumption, and higher reliability are the major design metrics for designing an SRAM cell. It is difficult to achieve an SRAM cell with stable operation at low voltage for low power consumption due to increasing variations in process, voltage, and temperature. It is proved that conventional 6 T fails to maintain its stability in scaled technology, particularly in deep-subthreshold regime. Furthermore, it does not support column bit-interleaving architecture. Therefore, it is very much prone to multibit soft error. In this paper, a double-ended read-decoupled ultralow-power 9-T SRAM cell (LP9T) is proposed, and the proposed cell supports the column bit-interleaving architecture. Because of read-decoupled technique, its noise tolerance is improved. To show the effectiveness of the proposed cell, it is compared with other recently published SRAM cells, namely, fully differential 8 T (FD8T), single-ended read-disturb-free 9 T (SEDF9T), and ultradynamic voltage scalable 10 T (UDVS10T). The proposed cell provides 1.2 $\times$ /2.3 $\times$ higher read current $I_{\mathrm{READ}}$ compared with UDVS10T/SEDF9T. Furthermore, LP9T shows 3.8 $\times$ /11.6 $\times$ improvement in read delay compared with FD8T/UDVS10T. The proposed cell achieves 3.9 $\times$ higher noise tolerance capability (i.e., read static noise margin (RSNM)) during read operation compared with FD8T. Moreover, LP9T consumes 2.1 $\times$ /2.1 $\times$ /4.9 $\times$ lower hold power $H_{\mathrm{Power}}$ during hold mode compared with FD8T/UDVS10T/SEDF9T. The proposed cell also exhibits 1.5 $\times$ /4.3 $\times$ /1.25 $\times$ narrower spread (i.e., more reliable) in $I_{\mathrm{READ}}/\text{RSNM}/H_{\mathrm{Power}}$ compared with UDVS10T/FD8T/SEDF9T. Furthermore, as the proposed cell supports bit-interleaving architecture, error checking and correction technique can be used to mitigate the issue related to multibit soft error. All these benefits are achieved by the LP9T at a cost of 1.17 $\times$ /1.17 $\times$ /1.25 $\times$ longer write delay compared with FD8T/UDVS10T/SEDF9T.

9-T SRAM Cell for Reliable Ultralow-Power Applications and Solving Multibit Soft-Error Issue

Full-Swing Gate Diffusion Input logic-Case-study of low-power CLA adder design

Low voltage operation of digital circuits continues to be an attractive option for aggressive power reduction. As standard SRAM bitcells are limited to operation in the strong-inversion regimes due to process variations and local mismatch, the development of specially designed SRAMs for low voltage operation has become popular in recent years. In this paper, we present a novel 9T bitcell, implementing a Supply Feedback concept to internally weaken the pull-up current during write cycles and thus enable low-voltage write operations. As opposed to the majority of existing solutions, this is achieved without the need for additional peripheral circuits and techniques. The proposed bitcell is fully functional under global and local variations at voltages from 250 mV to 1.1 V. In addition, the proposed cell presents a low-leakage state reducing power up to 60%, as compared to an identically supplied 8T bitcell. An 8 kbit SF-SRAM array was implemented and fabricated in a low-power 40 nm process, showing full functionality and ultra-low power.

A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM)

An SRAM memory cell with an internal supply feedback loop is provided herein. The memory cell includes a latch that has a storage node Q, a storage node QB, a supply node, and a ground node. The supply node is coupled via a gating device to a supply voltage and ground node is connected to ground. In addition, storage node Q is fed back via feedback loop into a control node of the gating device. In operation, writing into the memory cell may be carried out in a similar manner to dual port SRAM cells, utilizing one or two write circuitries and for writing into storage node Q and storage node QB respectively. Differently from standard SRAM cells, the feedback loop, by controlling the gating device is configured to weaken the write contention.

Ultra low power sram cell circuit with a supply feedback loop for near and sub threshold operation

A memory cell with an internal supply feedback loop is provided herein. The memory cell includes a latch having two storage nodes Q and QB, and a supply node. A gating device couples the supply node of the latch to the supply voltage. The gating device is controlled by a feedback loop coming from storage node QB. Due to the aforementioned asymmetric topology, the writing of logic “1” and the writing of logic “0” are carried out differently. Contrary to standard SRAM cells, in the hold states, only the QB storage node presents a valid value of stored data. The feedback loop cuts off the supply voltage for the latch such that the latch is no longer an inverting latch. By cutting off the supply voltage at the stable hold states, while maintaining readability of the memory cell, leakage currents associated with the hold states are eliminated altogether.

Ultra low power memory cell with a supply feedback loop configured for minimal leakage operation

As SRAMs continue to grow and comprise larger percentages of the area and power consumption in advanced systems, the need to minimize static currents becomes essential. This brief presents a novel 9T Quasi-Static RAM Bitcell that provides aggressive leakage reduction and high write margins. The quasi-static operation method of this cell, based on internal feedback and leakage ratios, minimizes static power while maintaining sufficient, albeit depleted, noise margins. This paper presents the concept of the novel cell, and discusses the stability of the cell under hold, read and write operations. The cell was implemented in a low-power 40 nm TSMC process, showing as much as a 12× reduction in leakage current at typical conditions, as compared to a standard 6T or 8T bitcell at the same supply voltage. The implemented cell showed full functionality under global and local process variations at nominal and low voltages, as low as 300 mV.

https://www.mdpi.com/2079-9268/1/1/204/pdf

A Minimum Leakage Quasi-Static RAM Bitcell

Being able to give a preliminary estimation of a solar field annual power output is of paramount importance, especially when dealing with large fields. The Cost of constructing such a field is very high, and the time it takes to repay itself is usually about a decade. It is shown that the 10-parameter solar cell model can be employed to suit any functional solar module which was tested in order to obtain its parameters. Then, the virtual parameters of a 10-parameter model of an entire panel (modeled as a large cell) can be obtained, and a running model for the entire field is deduced. To predict the field output, the sun elevation needs to be estimated annually as well. Using Woolf's equations, another Simulink model was constructed, delivering a 10 minute vector of samples of the sun's height all year-round.

http://ieeexplore.ieee.org/iel5/5655386/5661892/05662173.pdf

Omer Cohen

Papers

A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM)

Ultra low power sram cell circuit with a supply feedback loop for near and sub threshold operation

Ultra low power memory cell with a supply feedback loop configured for minimal leakage operation

A Minimum Leakage Quasi-Static RAM Bitcell

Predicting a solar field's power output, while considering environmental conditions