Reactive matching is extended to wide bandwidths using the impedance property of LC-ladder filters. In this paper, we present a systematic method to design wideband low-noise amplifiers. An SiGe amplifier with on-chip matching network spanning 3-10 GHz delivers 21-dB peak gain, 2.5-dB noise figure, and -1-dBm input IP3 at 5 GHz, with a 10-mA bias current.

A 3-10-Ghz low-noise amplifier with wideband LC-ladder matching network

This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

Radio-frequency (RF) integrated circuits are used for wireless communications and require transformers capable of transferring electrical energy at RF/microwave frequencies. Traditional on-chip RF transformer designs have complex fabrication schemes and offer limited performance scalability. Here we report on-chip RF/microwave transformers that are based on a self-rolled-up membrane platform. The monolithic nature and versatility of this platform allows us to create high-performance transformers while maintaining an ultra-compact device footprint and by using only planar processing. We also show that the performance of the three-dimensional RF transformers improves with scaling, which is in contrast to conventional planar designs. In particular, we observe a continuous rate of increase in the index of performance of our RF transformers as we scale up the turns ratio. This behaviour is attributed to the almost ideal mutual magnetic coupling inherent to the self-rolled-up membrane three-dimensional architecture.

Three-dimensional radio-frequency transformers based on a self-rolled-up membrane platform

This paper reports the design and analysis of 21-29-GHz CMOS low-noise amplifier (LNA), balun and mixer in a standard 0.18-μm CMOS process for ultra-wideband automotive radar systems. To verify the proposed LNA, balun, and mixer architectures, a simplified receiver front-end comprising an LNA, a double-balanced Gilbert-cell-based mixer, and two Marchand baluns was implemented. The wideband Marchand baluns can convert the single RF and local oscillator (LO) signals to nearly perfect differential signals over the 21-29-GHz band. The performance of the mixer is improved with the current-bleeding technique and a parallel resonant inductor at the differential outputs of the RF transconductance stage. Over the 21-29-GHz band, the receiver front-end exhibits excellent noise figure of 4.6±0.5 dB, conversion gain of 23.7±1.4 dB, RF port reflection coefficient lower than -8.8 dB, LO-IF isolation lower than -47 dB, LO-RF isolation lower than -55 dB, and RF-IF isolation lower than -35.5 dB. The circuit occupies a chip area of 1.25×1.06 mm2, including the test pads. The dc power dissipation is only 39.2 mW.

Design and Analysis of a 21–29-GHz Ultra-Wideband Receiver Front-End in 0.18- $\mu$ m CMOS Technology

A novel on-chip transformer configuration that gives an identical inductor pair, a higher individual coil self-resonant frequency (SRF), and excellent area efficiency are presented. This technique involves the unique way of inter-crossing the transformer's primary and secondary coils using multiple metallization layers. Truly symmetrical transformer configuration (100%) is demonstrated using minimum die size. Thus, a true 1 : 1 transformer has been realized on silicon. The effects of the parasitic within the transformer are represented by an equivalent-circuit model. Accurate semiempirical expressions describing the circuit components are provided based on the various layout parameters. Of all the transformer structures presented, the two designs occupying the minimum silicon area by a factor of > 2t have been selected for performance evaluation of the SRF, coupling coefficient, input impedance, quality factor, and inductance. The transmission line transformer mode has also been studied to examine the designs' performance in the differential mode. The second proposed design reported in this paper, with enhancements in S21 and k performance, is created by adding a unique routing technique onto the first proposed structure. The method presented is fully compatible with the standard foundry CMOS processes. The silicon data reported in this study are based on chartered semiconductor manufacturing's 0.13-mum RF CMOS technology node.

https://dr.ntu.edu.sg/bitstream/10220/6261/1/Fully%20symmetrical%20monolithic%20transformer%20%28true%201-1%29%20for%20silicon%20RFIC.pdf

Fully Symmetrical Monolithic Transformer (True 1 : 1) for Silicon RFIC

A broadband and scalable lumped-element model for silicon on-chip transformers is presented. Model elements are driven from layout and process technology specifications. We provide simple and accurate expressions for evaluating the self inductance and the mutual coupling coefficient. The effects of various layout parameters, including transformer area, number of turns, and turns ratio, on transformer electrical response have been investigated. Model accuracy is demonstrated by comparing simulated and measured S-parameters, minimum insertion loss, quality factor, coils inductance, and magnetic coupling of several transformers with a wide range of configurations

Modeling and Characterization of On-Chip Transformers for Silicon RFIC

We present a compact and scalable model for on-chip transformers fabricated in silicon IC technology The model is driven from the layout and the process technology specifications It is suitable for design optimization and circuit simulation EM-simulation is used to validate the model The proposed model shows excellent agreement with EM-simulation over a large frequency range (1-15 GHz)

Modeling of integrated monolithic transformers for silicon RF IC

The most efficient technique, based on LC ladder filtering, providing wide input matching in UWB LNA is first reviewed. Implemented with integrated inductors in a cascode topology, the circuit covers the 6 to 10 GHz upper frequency of European UWB and achieves an 8 dB maximum gain and 7.5 dB minimum noise figure for a 9 mW power consumption. A transformer implementation of this Inductive Degeneration LC Filtering cascode architecture is also proposed. It leads to reduce by 50% the number of integrated inductors. Providing a 13 dB maximum gain from 3 to 5 GHz, the lower band of UWB, the circuit exhibits a 4 dB minimum NF under 9 mW power consumption.

UWB LNAs using LC ladder and transformers for input matching networks

A low noise amplifier (LNA) for ultra-wideband (UWB) systems operating in 3~5GHz frequency range is presented. The LNA circuit is a cascade topology with inductively degeneration transistor. A new input impedance matching network based on monolithic transformers was proposed to overcome to the problem of broadband matching without degrading the noise performance and power delivery. The LNA achieves a power gain of 13 dB with an input matching of -9dB over the band, , a -3 dB bandwidth of 2.9 - 7.8 GHz, an input IP3 of -2dBm, a minimum noise figure (NF) of 4.0 - 4.6dB across the entire bandwidth, while consuming 9 mW at 1.8V supply

3~5-GHz SiGe UWB LNA Using On-Chip Transformer for Broadband Matching

A concurrent dual-band low noise amplifier (LNA) for the 802.11a/g WLAN applications is presented. The circuit is designed in standard SiGe BiCMOS process from STMicroelectronics. The LNA circuit is a cascade topology with inductively degeneration transistor. A new input impedance matching network based on monolithic transformers was proposed to overcome to the problem of dual-band matching without degrading the noise performance and power delivery. The dual-band LNA provides a narrow band gain of 18.3 dB and 15.2 dB at 2.45 GHz and 5.5 GHz, simultaneously. It achieves input returns losses of -24 dB and -28 dB, a noise figure of 2.26 dB and 3.2 dB at these two bands, respectively. The LNA consumes 12 mW from a single 2 V supply.

Ouail El-Gharniti

Papers

Modeling and Characterization of On-Chip Transformers for Silicon RFIC

Modeling of integrated monolithic transformers for silicon RF IC

UWB LNAs using LC ladder and transformers for input matching networks

3~5-GHz SiGe UWB LNA Using On-Chip Transformer for Broadband Matching

Concurrent Dual-Band Low Noise Amplifier for 802.11a/g WLAN applications