An injection-locked oscillator topology is presented, based on MOS switches directly coupled to the LC tank of well-known LC oscillators. The direct injection-locking scheme features wide locking ranges, a very low input capacitance, and highest frequency capability. The direct locking and the tradeoff between power consumption and tank quality factor is verified through three test circuits in 0.13-/spl mu/m standard CMOS, aiming at input frequency ranges of 50, 40, and 15 GHz. The 40- and 50-GHz dividers consume 3 mW with locking ranges of 80 MHz and 1.5 GHz. The 15-GHz divider consumes 23 mW and features a locking range of 2.8 GHz.

A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider

Integrated-Circuit Fabrication. Active Devices in Integrated Circuits. Passive Components: Diodes, Resistors, and Capacitors. Bias Circuits. Basic Gain Stages. Analog Design with MOS Technology. Operational Amplifiers. Wideband Amplifiers. Analog Multipliers and Modulators. Voltage Regulators. Integrated-Circuit Oscillators and Timers. Phase-Locked-Loop Circuits. Integrated-Circuit Filters. Data Conversion Circuits: Digital-To-Analog Converters. Data Conversion Circuits: Analog-To-Digital Converters. Index.

Bipolar and MOS Analog Integrated Circuit Design

https://repository.upenn.edu/cgi/viewcontent.cgi?article=1145&context=be_papers

The inhibition of Staphylococcus epidermidis biofilm formation by vancomycin-modified titanium alloy and implications for the treatment of periprosthetic infection.

This paper presents the results of tests that demonstrate the feasibility of using piezoelectric (PZT) ceramics to generate in vivo electrical energy for orthopedic implants. Sensors encapsulated within implants could provide in vivo diagnostic capabilities such as the monitoring of implant duty (i.e., walking) cycle, detecting abnormally asymmetric or high forces, sensing misalignment and early loosening, and early detection of wear. Early diagnosis of abnormalities or impending failure is critical to minimize patient harm. However, the routine use of sensors and microprocessors embedded within orthopedic implants for diagnostic and monitoring purposes has been limited by the lack of a long-term self-contained power source capable of lasting the expected 20-year implant lifetimes. By embedding PZT materials within orthopedic implants, a small amount of the mechanical energy generated during normal physical activity can be converted into useful electrical energy. This in vivo energy source can power embedded microprocessors and sensors for a broad range of biomedical uses. The current work investigates the application of this technology to total knee replacement (TKR) implants, but it is applicable to many other implanted biomedical devices.

The use of piezoelectric ceramics for electric power generation within orthopedic implants

The review makes a brief overview of traditional methods of measurement of electric current and shows in more detail relatively new types of current sensors. These include Hall sensors with field concentrators, AMR current sensors, magneto-optical and superconducting current sensors. The influence of the magnetic core properties on the error of the current transformer shows why nanocrystalline materials are so advantageous for this application. Built-in CMOS current sensors are important tools for monitoring the health of integrated circuits. Of special industrial value are current clamps which can be installed without breaking the measured conductor. Parameters of current sensors are also discussed, including geometrical selectivity. This parameter specific for current sensors means the ability to suppress the influence of currents external to the sensor (including the position of the return conductor) and also suppress the influence on the position of the measured conductor with respect to the current.

/pdf/electric-current-sensors-a-review-4b35763ekq.pdf

Electric current sensors: a review

Concept, design and fabrication of smart orthopedic implants

A broadband and scalable lumped-element model for silicon on-chip transformers is presented. Model elements are driven from layout and process technology specifications. We provide simple and accurate expressions for evaluating the self inductance and the mutual coupling coefficient. The effects of various layout parameters, including transformer area, number of turns, and turns ratio, on transformer electrical response have been investigated. Model accuracy is demonstrated by comparing simulated and measured S-parameters, minimum insertion loss, quality factor, coils inductance, and magnetic coupling of several transformers with a wide range of configurations

Modeling and Characterization of On-Chip Transformers for Silicon RFIC

This work reports on the implementation of a 2.4 GHz ultra low power (ULP) low noise amplifier (LNA) in a standard CMOS 0.13 µm process. The proposed design methodology consists in optimizing the tradeoff between RF performances and current consumption of the MOS transistor. The supply of the circuit controlled by a 3bits DAC varies from 0.4 to 0.6 V. This digital tuning allows maximizing the figure of merit of the LNA. The approach yields the operating point within the sweet spot region of the amplifying transistors. Experimental results of the circuit indicate a power dissipation of 60 µW@0.4V, a noise figure of 5.3 dB, and a forward gain of 13.1 dB. The IIP3 and ICP1 are −12 dBm and −19 dBm, respectively. This works aims the development of a complete RF front end for micro-watt radio.

A 60µW LNA for 2.4 GHz wireless sensors network applications

The paper describes work done on a LC-VCO to linearize its frequency-voltage (Kvco) characteristic in order to extend its versatility. The technology used is a standard 0.13 /spl mu/m CMOS supplied by 1.2 V. The optimization is made on the varactor stage of the resonator and gives a nearly constant Kvco (140/spl plusmn/10 MHz/V from 2.36 GHz to 2.44 GHz), in spite of the MOS varactor non-linear characteristic, with still a good pushing (9 MHz/V) and constant phase noise (-126 dBc/Hz at 3 MHz offset).

Distributed MOS varactor biasing for VCO gain equalization in 0.13 /spl mu/m CMOS technology

A self-testable and highly reliable low noise amplifier designed in 0.13 m CMOS technology is presented in this paper. This reliable LNA could be used to design the front-end of critical nodes in wireless local area networks to ensure data transmission. The LNA test, based on a built-in self test methodology, monitors its behavior. The test circuit is composed of one sensor and one biasing voltage sensor, and it offers high fault coverage. The high reliability is ensured by the use of redundancies. The LNA works under a 0.9 V supply voltage and the test chip has RF characteristics suitable for 802.11b/g applications. Parametric faults are injected and detected to demonstrate the efficiency of the BIST circuitry. Thanks to the switching on redundant blocks, performances are maintained and hence this proves the reliability of the methodology proposed.

J-B. Begueret

Papers

Concept, design and fabrication of smart orthopedic implants

Modeling and Characterization of On-Chip Transformers for Silicon RFIC

A 60µW LNA for 2.4 GHz wireless sensors network applications

Distributed MOS varactor biasing for VCO gain equalization in 0.13 /spl mu/m CMOS technology

Design of a 0.9 V 2.45 GHz Self-Testable and Reliability-Enhanced CMOS LNA