There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

(1987). Applied Probability and Queues. Journal of the Operational Research Society: Vol. 38, No. 11, pp. 1095-1096.

https://link.springer.com/content/pdf/10.1057%2Fjors.1987.184.pdf

Applied Probability and Queues

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

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私の computer 環境

A wireless telecommunication system comprises base stations for communicating with terminal devices. One or more base stations support a power boost operating mode in which a base station's available transmission power is concentrated in a subset of its available transmission resources to provide enhanced transmission powers as compared to transmission powers on these transmission resources when the base station is not operating in the power boost mode. A base station establishes an extent to which one or more base stations in the wireless telecommunications system support the power boost operating mode conveys an indication of this to a terminal device. The terminal device receives the indication and uses the corresponding information to control its acquisition of a base station of the wireless telecommunication system, for example by taking account of which base stations support power boosting and/or when power boosting is supported during a cell attach procedure.

Telecommunications apparatus and methods

Specialized hardware accelerators can significantly improve the performance and power efficiency of compute systems. In this paper, we focus on hardware accelerators for graph analytics applications and propose a configurable architecture template that is specifically optimized for iterative vertex-centric graph applications with irregular access patterns and asymmetric convergence. The proposed architecture addresses the limitations of the existing multi-core CPU and GPU architectures for these types of applications. The SystemC-based template we provide can be customized easily for different vertex-centric applications by inserting application-level data structures and functions. After that, a cycle-accurate simulator and RTL can be generated to model the target hardware accelerators. In our experiments, we study several graph-parallel applications, and show that the hardware accelerators generated by our template can outperform a 24 core high end server CPU system by up to 3x in terms of performance. We also estimate the area requirement and power consumption of these hardware accelerators through physical-aware logic synthesis, and show up to 65x better power consumption with significantly smaller area.

/pdf/energy-efficient-architecture-for-graph-analytics-sxol0hx2hg.pdf

Energy efficient architecture for graph analytics accelerators

Transient errors are one of the major reasons for system downtime in many systems. While prior research has mainly focused on the impact of transient errors on datapath, caches and main memories, the register file has largely been neglected. Since the register file is accessed very frequently, the probability of transient errors is high. In addition, errors in it can quickly spread to different parts of the system, and cause application crash or silent data corruption. This paper addresses the reliability of register files in superscalar processors. Particularly, we propose to duplicate actively used physical registers in unused physical registers. The rationale behind this idea is that if the protection mechanism (parity or ECC) used for the primary copy indicates an error, the duplicate can provide the data as long as it is not corrupted. We implement two types of strategies based on this register duplication idea. In the "conservative strategy," we limit ourselves with the given register usage behavior, and duplicate register contents only on otherwise unused registers. Consequently, there is no impact on the original performance when there is no error, except for the protection mechanism used for the primary copy. Our experiments with two different versions of this strategy show that, with the more powerful conservative scheme, 78% of the accesses are to the physical registers with duplicates .The "aggressive strategy" sacrifices some performance to increase the number of register accesses with duplicates. It does so by marking the registers not used for a long time as "dead" and using them for duplicating actively used registers. The experiments with this strategy indicate that it takes the fraction of the reliable register accesses to 84%, and degrades the overall performance by only 0.21% on the average.

/pdf/increasing-register-file-immunity-to-transient-errors-cy9ay0xlh3.pdf

Increasing Register File Immunity to Transient Errors

Ever shrinking technologies in VLSI era made it possible to place several modules onto a single die. However, the need for the new communication methods has also increased dramatically since traditional bus-based systems suffer from signal propagation delays, signal integrity, and scalability. Network-on-Chip (NoC) is the biggest step towards the communication bottleneck of System-on-Chip (SoC) architectures. In this paper, we present an Integer Linear Programming (ILP) formulation for application mapping onto mesh based Network-on-Chips to minimize the energy consumption of the system. The proposed method obtains optimal or close to optimal results within the given computation time limit. We also experimentally investigate the impact of the size of the mesh architecture on the application mapping and total communication.

/pdf/an-ilp-formulation-for-application-mapping-onto-network-on-1hdo5cqixn.pdf

An ILP formulation for application mapping onto Network-on-Chips

Systems and methods for dynamically adjusting the transmission time interval (TTI) for a communications system are presented. The described aspects provide for dynamically adjusting the TTI in a communication session between a base station or nodeB and a wireless device or user equipment between a shorter TTI, which can provide increased data throughput and lower power consumption, and a longer TTI, which can provide more rugged communication link connections. By dynamically adjusting the TTI, the communications link can be optimized for the given communication channel conditions. Determinations, based on indicia related to the communications system conditions, can be employed in dynamic TTI adjustment. These determinations can be formed centrally at the Radio Network Controller (RNC), at the RNC supplemented with user equipment (UE) available information, or formed in a distributed manner between the RNC and UE across a communications system.

Method and apparatus for dynamic adjustment of uplink transmission time

Certain aspects of the present disclosure relate to techniques for aggregating data from a wireless wide area network (WWAN) and wireless local area network (WLAN). In some aspects, a packet convergence entity (e.g., PDCP layer entity) communicates with first and second radio access technology (RAT) links. The packet convergence entity may determine from which of the first and second RAT links a data packet is received and may monitor a sequence number value of each of the received data packets. The packet convergence entity may perform one or more actions based on a determination that the data packets are received out of order. For example, the packet convergence entity may deliver the data packets to an upper layer entity as they are received (e.g., in order or out of order), may reorder the data packets and ignore data packet losses, and/or may request retransmissions of missing data packets.

Ozcan Ozturk

Papers

Energy efficient architecture for graph analytics accelerators

Increasing Register File Immunity to Transient Errors

An ILP formulation for application mapping onto Network-on-Chips

Method and apparatus for dynamic adjustment of uplink transmission time

Techniques for aggregating data from wwan and wlan