An AlGaN/GaN high-electron-mobility transistor (HEMT) with a novel source-connected air-bridge field plate (AFP) is proposed. The device features a metal field plate (FP) that jumps from the source over the gate region and lands between the gate and drain. The fabrication process is based on a commercially available radio-frequency GaN-on-SiC technology. Device characteristics for this work were optimized via layout changes only. When compared to a similar-sized HEMT device with a conventional FP structure, the AFP not only minimizes the parasitic gate-to-source capacitance but also exhibits a higher off-state breakdown voltage and one order of magnitude lower drain leakage current. In a device with a gate-to-drain distance of 6 μm and a gate length of 0.8 μm, a three-times-higher forward blocking voltage of 375 V was obtained at VGS = -5 V. In contrast, a similar-sized HEMT with a conventional FP can only achieve a breakdown voltage no higher than 125 V using this process, regardless of device dimensions. The specific on-resistance for the device with the proposed AFP is 0.58 mΩ·cm2 at VGS = 0 V, which compares favorably with 0.79 mΩ·cm2 for the best device with a conventional FP.

Breakdown-Voltage-Enhancement Technique for RF-Based AlGaN/GaN HEMTs With a Source-Connected Air-Bridge Field Plate

This paper provides an overview of the fundamental operating principles of power semiconductor devices and reviews the state-of-the-art power device technologies which are most relevant to the realization of power supply on chip and power supply in package solutions. Power switching devices are divided into four categories low-voltage discrete transistors, high-voltage discrete transistors, low-voltage power ICs, and high-voltage power ICs. Advantages and disadvantages of different device technologies are compared and analyzed. Future technology trends are discussed.

Review of Silicon Power Semiconductor Technologies for Power Supply on Chip and Power Supply in Package Applications

The combination of low specific on-resistance, Sp.R DS(on ), and low gate charge, Q G and Q GD , has been achieved by applying a superjunction approach to an n-type 30V vertical trench power MOSFET structure. Whereas lateral technologies have low Q G and Q GD figures of merit with poor Sp.R DS(on ) (due to cell pitch limitations) and split-gate RSO structures have excellent Sp.R DS(on) and Q GD FOM at the expense of the Q G FOM (due to creation of additional C GS ), the superjunction structure has been shown to be achieving benchmark performance in all three of these performance indicators simultaneously. For a 30V rated device, specific on-state resistances of 3.9mOmm2 (V GS =10V) and 6.5mΩmm2 (V GS =4.5V) have been demonstrated along with switching figures of merit as low as 22.7mΩnC (RDS(on)×QG) and 4.6mΩnC (R D S(on)×QGD). The result is a technology that combines the best aspects of both vertical trench and lateral power MOSFET structures.

Low voltage TrenchMOS combining low specific R DS(on) and Q G FOM

We propose a new trench gate power MOSFET with poly-Si spacers formed in the trench to work as gate material. This approach reduces the total gate charge and gate-to-drain capacitive coupling without affecting any other device performance parameter. Using 2-D numerical simulation on a ~25-V trench gate MOSFET, we have shown that using a 50-nm-wide spacer gate in a 1×1 μm trench may give >; 40% reduction in the gate-to-drain charge compared with the conventional device. The proposed technique has been shown to be better than the other techniques proposed earlier for reducing gate charge as it does not affect the gate control of the accumulation region charge or any other performance parameter, e.g., breakdown voltage, and can be implemented along with any of the existing techniques.

Polysilicon Spacer Gate Technique to Reduce Gate Charge of a Trench Power MOSFET

In this paper, a high-current dc-dc power supply in package is reported with an emphasis on the design aspects of the low- and high-side power MOSFETs embedded in the power module. A new NexFET structure with its source electrode on the bottom side of the die (source down) is designed to enable an innovative stacked-die PSiP technology with significantly reduced parasitic inductance and package footprint. A gate voltage pulldown circuitry monolithically integrated in the low-side NexFET is introduced to effectively prevent shoot-through faults even when a very low gate threshold voltage is used to reduce conduction and body diode reverse-recovery-related power losses. In addition, an asymmetric gate resistor circuitry is monolithically integrated in the high-side NexFET to minimize voltage ringing at the switch node. With all these novel device technology improvements, the new power supply in package module delivers a significant improvement in efficiency and offers an excellent solution for future high-frequency, high-current-density dc-dc converters.

Advanced Low-Voltage Power MOSFET Technology for Power Supply in Package Applications

A new generation of Power MOSFET technology has been introduced. The devices are manufactured in a standard 0.35µm CMOS production line with only few process modules being adapted for the requirements of vertical power transistors with a 2x improvement in Figure of Merit (FOM). This improvement results mainly from the reduction in Miller capacitance.

http://pwrsocevents.com/wp-content/uploads/2010-presentations/202%20-%20Shuming%20Xu,%20Sameer%20Pendharkar%20-%20NexFET%20Technology%20-%20New%20Technology%20Enables%20High%20Power%20Density.pdf

NexFET a new power device

In this paper, an integrated NexFET power module is presented to meet requirements on next-generation, high efficiency and high current density DC-DC converters for computer applications. The new power module uses an innovative stacked-die package technology, implements low Vth power MOSFET in the low-side position, and introduces monolithically integrated components to avoid shoot-through and minimize voltage ringing at the switch node. In synchronous buck application, this power module achieves over 90% efficiency and low switch node ringing at high output current rating (25A) and high operation frequency (1MHz) under 12V input and 1.3V output condition.

NexFET generation 2, new way to power

Efficiency and power loss in the microelectronic devices is a major issue in power electronics applications. The engineers are challenged every year to increase power density and at the same time reduce the amount of power dissipated in the applications to keep the maximum temperatures under specifications. This situation drives a constant demand for better efficiencies in smaller packages. Traditional approaches to improve efficiency in DC/DC synchronous buck converters include reducing conduction losses in the MOSFETs through lower RDS(ON) devices and lowering switching losses through low-frequency operation. However the incremental improvements in RDS(ON) are at a point of diminishing returns and low RDS(ON) devices have large parasitic capacitances that do not facilitate the high-frequency operation required to improve power density. The drive for higher efficiency and increased power in smaller packages is being addressed by advancements in both silicon and packaging technologies. The NexFET Power Block combines these two technologies to achieve higher levels of performance, and in half the space versus discrete MOSFETs. This article explains these new technologies and highlights their performance advantage.

Innovative 3D integration of power MOSFETs for synchronous buck converters

Integration in power semiconductor devices has been always a challenge for technologists. This occurs mainly because the integration process increases the power density with negative consequences in the temperature of the devices which deteriorate the electrical and reliability performance in comparison with discrete approach. In order to successfully integrate power microelectronic devices one needs to have semiconductor solutions with extremely good efficiency to dissipate small quantities of heat and package solutions that can conduct extremely well the heat generated so the junction temperature of the device does not exceed the maximum temperatures under specifications. Traditional approaches to improve efficiency in DC/DC synchronous buck converters include reducing conduction losses in the MOSFETs through lower RDS(ON) devices and lowering switching losses through low-frequency operation. However the incremental improvements in RDS(ON) are at a point of diminishing returns and low RDS(ON) devices have large parasitic capacitances that do not facilitate the high-frequency operation required to improve power density. The drive for higher efficiency and excellent thermal performance to achieve high degree of integration is being addressed by advancements in both silicon and packaging technologies. In this paper we present the Power Stage concept, the technology we developed in the silicon and packaging fronts in order to integrate a half bridge DC-DC synchronous Buck converter with a gate driver IC. The NexFET Power Stage achieves higher levels of performance and integration, and in half the space versus discrete MOSFETs. This article explains these new technologies and highlights their performance advantage.

Integration of power semiconductors devices: Synchronous buck converters in a package

Integration of power semiconductor devices poses many challenges, i.e. in a synchronous buck converter package where stacking multiple dies concentrates heat dissipation within a given area, the effects of which could result in elevated junction temperatures and degradation in its performance and long term reliability. To counter these challenges one needs to have a semiconductor solution with extremely good efficiency and packaging solutions that can conduct heat extremely well in multiple directions. Since TI NexFET™ addresses the silicon efficiency and performance; we focused our work on enhancing the thermal performance of a 3D power package. By implementing new design modifications in the clips and reducing the mold cap thickness, we were able to improve the overall thermal performance of stacked synchronous buck converters. There are many methods to improve the thermal performance of the 3D power package and in this paper we will present three methods evaluated for achieving that.

Ozzie Lopez

Papers

NexFET a new power device

NexFET generation 2, new way to power

Innovative 3D integration of power MOSFETs for synchronous buck converters

Integration of power semiconductors devices: Synchronous buck converters in a package

Methods to enhance the thermal performance of a 3D power package