An improved fast acquisition phase-frequency detector (PFD) for Phase-Locked Loop (PLL) is presented. The proposed PFD completely eliminates the blind zone, which is caused by the missing input edge during reset pulse. It has a linear output range and a saturated output when the phase error is in [0, π] and [π, 2π]. The simulation results with the SMIC 65nm CMOS technology file show that, comparing with the published works, the proposed nonlinear gain PFD has a faster lock process, and improves the maximum operating frequency to as higher as 1GHz.

An improved fast acquisition PFD with zero blind zone for the PLL application

A multiphase, delay-locked loop (DLL) based frequency synthesizer is designed for harmonic rejection mixing in reconfigurable radios. This frequency synthesizer uses a 1 GHz input reference frequency, and achieves ≤ 20ns settling time by utilizing a wide loop bandwidth. The circuit has been designed in 0.13-μm CMOS technology. It is designed for a frequency range of 500 MHz to 3 GHz with stuck/harmonic lock removal assist.

Differential multi-phase DLL for reconfigurable radio frequency synthesizer

Data stability and power consumption have been reported two important issues with scaling of CMOS technology. In this paper, we have revisited these issues on 6T, 7T, 8T, 9T, 10T SRAM cells individually and a comparative analysis has been done based on different parameters like read delay, write delay, power consumption and static noise margin (SNM). The read/write delay and power consumption has been found 0.671/0.267 ns, 1.69 µW for 6T SRAM cell, 0.456/0.752 ns, 1.09 µW for 7T SRAM cell, 0.517/0.392 ns, 1.82 µW for 8T SRAM cell, 0.388/0.181 ns, 1.3 µW for 9T SRAM cell and 0.167/0.242 ns, 2.01 µW for 10T SRAM cell respectively. SNM has been calculated 0.4 V for 6T SRAM cell, 0.375 V for 7T SRAM cell, 0.65 V for 8T SRAM cell, 0.65 V for 9T SRAM cell and 0.6 V for 10T SRAM cell. All the circuit of SRAM cells and their layout has been designed using Cadence virtuoso ADE tool and Cadence virtuoso layout suite respectively using 180 nm CMOS technology. The post layout simulation results have been shown a good agreement with pre layout simulation results.

Comparative Study of 7T, 8T, 9T and 10T SRAM with Conventional 6T SRAM Cell Using 180 nm Technology

Leakage power is a major issue for short channel devices. As the technology is shrinking (i.e., 180nm, 90nm, 45nm. etc.) the leakage current is increasing very fast. So, several methods and techniques have been proposed for leakage reduction in CMOS digital integrated circuits. Leakage power dissipation has become a sizable proportion of the total power dissipation in integrated circuit. This paper demonstrates the ideas of 6T, 8T and 10T models with sleep transistors. This proposed SRAM cells give the advantages over basic 6T, 8T and 10T transistor models. The SRAM cell with sleep transistor shows better leakage reduction approach than stack approaches. Here in this paper Analog environment virtuoso (cadence) simulator is used for analysis of the power associated with CMOS SRAM cell for 180nm technology.

Analysis of leakage current and leakage power reduction during write operation in CMOS SRAM cell

The design of Low Power Low Glitch Dynamic Phase Frequency Detector (PFD) is proposed in this paper. The dynamic PFD helps Delay Locked Loop (DLL) to detect the phase error information in form of pulses at high frequency and plays an important role for improving the performance of complete DLL block. A Low Power and Low glitch phase frequency detector is proposed at 180 nm technology node using GPDK180 library with supply voltage VDD=1.8 V in Cadence Virtuoso for schematic composer, Spectre tool for simulations and Cadence Layout editor for layout. By simulating the proposed PFD block, significant reduction in area and power dissipation was observed. Also phase sensitivity has improved significantly and there is no reset path present. It was observed that the proposed dynamic PFD has very low glitch as compared to conventional D flip-flop based PFD. This PFD is designed for low power Delay Locked Loop.

A novel design of an efficient Low Power Phase Frequency Detector for Delay Locked Loop

This paper present the design scheme of a phase frequency detector (PFD) which uses domino logic. The PFD is capable of working in gigahertz range frequency with reduced the dead zone as the reset path is increased using the inverters. The linear detection range is also increased of this PFD. In particular maximum operating frequency of PFD is discussed. The proposed PFD has simple structure with using 26 transistors. It can be operated at 1.8 V supply using 0.18 micron CMOS technology. This PFD is designed for RF range delay locked loop.

Phase frequency detector of delay locked loop at high frequency

CMOS SRAM cell is very less power consuming and have less read and write time. Higher cell ratios can decrease the read and write time and improve stability. PMOS transistor with less width reduces the power consumption. This paper implements 6T SRAM cell with reduced read and write time, area and power consumption. It has been noticed often that increased memory capacity increases the bit-line parasitic capacitance which in turn slows down voltage sensing and make bit-line voltage swings energy expensive. This result in slower and more energy hungry memories.. In this paper Two SRAM cell is being designed for 4 Kb of memory core with supply voltage 1.8 V. A technique of global bit line is used for reducing the power consumption and increasing the memory capacity.

P. Deshpande

Papers

Phase frequency detector of delay locked loop at high frequency

VLSI design and analysis of low power 6T SRAM cell using cadence tool