Proceedings ArticleDOI
VLSI design and analysis of low power 6T SRAM cell using cadence tool
Kavita Khare,Nilay Khare,V.K. Kulhade,P. Deshpande +3 more
- pp 117-121
TLDR
In this paper, a technique of global bit line is used for reducing the power consumption and increasing the memory capacity of two SRAM cells for 4 Kb memory core with supply voltage 1.8 V.Abstract:
CMOS SRAM cell is very less power consuming and have less read and write time. Higher cell ratios can decrease the read and write time and improve stability. PMOS transistor with less width reduces the power consumption. This paper implements 6T SRAM cell with reduced read and write time, area and power consumption. It has been noticed often that increased memory capacity increases the bit-line parasitic capacitance which in turn slows down voltage sensing and make bit-line voltage swings energy expensive. This result in slower and more energy hungry memories.. In this paper Two SRAM cell is being designed for 4 Kb of memory core with supply voltage 1.8 V. A technique of global bit line is used for reducing the power consumption and increasing the memory capacity.read more
Citations
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Book ChapterDOI
Comparative Study of 7T, 8T, 9T and 10T SRAM with Conventional 6T SRAM Cell Using 180 nm Technology
TL;DR: A comparative analysis has been done based on different parameters like read delay, write delay, power consumption and static noise margin (SNM) on 6T, 7T, 8T, 9T, 10T SRAM cells individually and a good agreement with pre layout simulation results has been shown.
Proceedings ArticleDOI
Analysis of leakage current and leakage power reduction during write operation in CMOS SRAM cell
TL;DR: Analog environment virtuoso (cadence) simulator is used for analysis of the power associated with CMOS SRAM cell for 180nm technology and theSRAM cell with sleep transistor shows better leakage reduction approach than stack approaches.
Journal ArticleDOI
Leakage immune modified pass transistor based 8t SRAM cell in subthreshold region
TL;DR: Comparison analysis shows that the proposed 8T SRAM cell with access pass gates replaced with modified PMOS pass transistor logic has a significant improvement, thereby achieving high cell stability at 45nm technology node.
Proceedings ArticleDOI
Analysis of SRAM cell designs for low power applications
TL;DR: A convincing power reduction is achieved in a SRAM cell with minimum critical path delay using sleep transistor technique, and two different techniques are analyzed for the same namely forced stack transistor technique andSleep transistor technique.
Proceedings ArticleDOI
A novel low leakage and high density 5T CMOS SRAM Cell in 45nm technology
TL;DR: In this article, a new 5T SRAM cell with fast performance, high density and low power consumption is proposed, which consumes less power and has less read and write time than conventional six-transistor SRAM cells.
References
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Journal ArticleDOI
Static-noise margin analysis of MOS SRAM cells
TL;DR: In this article, the stability of both resistor-load (R-load) and full-CMOS SRAM cells is investigated analytically as well as by simulation, and explicit analytic expressions for the static-noise margin (SNM) as a function of device parameters and supply voltage are derived.
Journal ArticleDOI
Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies
TL;DR: This paper analyzes the read stability N-curve metrics and compares them with the commonly used static noise margin (SNM) metric defined by Seevinck, and demonstrates that the new metrics provide additional information in terms of current, which allows designing a more robust and stable cell.
Journal ArticleDOI
A read-static-noise-margin-free SRAM cell for low-V/sub dd/ and high-speed applications
TL;DR: A read-static-noise-margin-free SRAM cell consists of seven transistors, several of which are low, NMOS transistors used to achieve both low-V/sub dd/ and high-speed operation.
Journal ArticleDOI
A low-power SRAM using hierarchical bit line and local sense amplifiers
Byung-Do Yang,Lee-Sup Kim +1 more
TL;DR: In this article, a low power SRAM using hierarchical bit line and local sense amplifiers (HBLSA-SRAM) was proposed to reduce both capacitance and write swing voltage of bit lines.
Journal ArticleDOI
Low-power SRAM design using half-swing pulse-mode techniques
Ken Mai,T. Mori,Bharadwaj Amrutur,Ron Ho,Bennett Wilburn,Mark Horowitz,I. Fukushi,T. Izawa,S. Mitarai +8 more
TL;DR: In this paper, a half-swing pulse-mode gate family that uses reduced input signal swing without sacrificing performance is described. But the performance of the gate is limited by the high-capacitance predecode lines, write bus lines, and bit lines.
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