In linear IC's fabricated in a low-voltage CMOS technology, the reduction of the dynamic range due to the dc offset and low frequency noise of the amplifiers becomes increasingly significant. Also, the achievable amplifier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing. In this paper, some old and some new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain resulting in a nonideal virtual ground at the input.

Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization

A battery pack and a method of operating a battery system. The battery pack includes a rechargeable battery and a processor for monitoring the battery during charging and discharging. The processor receives data values representing the battery voltage, temperature and current, and the processor performs a series of calculations using those data values. In one of these calculations, the processor determines the actual full capacity of the battery. Preferably, the processor also keeps track of an uncertainty value that represents an uncertainty in the capacity of the battery; and the processor calculates the actual full capacity of the battery at the end of each discharge cycle if, at that time, the uncertainty value is less than a given percentage of a nominal full capacity of the battery.

Battery pack having a processor controlled battery operating system

The latched comparator is a building block of virtually all analog-to-digital converter architectures. It uses a positive feedback mechanism to regenerate the analog input signal into a full-scale digital level. The large voltage variations in the internal nodes are coupled to the input, disturbing the input voltage-this is usually called kickback noise. This brief reviews existing solutions to minimize the kickback noise and proposes two new ones. HSPICE simulations of comparators implemented in a 0.18-/spl mu/m technology demonstrate their effectiveness.

Kickback noise reduction techniques for CMOS latched comparators

Analog-Digital (A/D) converters used in instrumentation and measurements often require high absolute accuracy, including very high linearity and negligible dc offset. The realization of high-resolution Nyquist-rate converters becomes very expensive when the resolution exceeds 16 bits. The conventional delta-sigma (/spl Delta//spl Sigma/) structures used in telecommunication and audio applications usually cannot satisfy the requirements of high absolute accuracy and very small offset. The incremental (or integrating) converter provides a solution for such measurement applications, as it has most advantages of the /spl Delta//spl Sigma/ converter, yet is capable of offset-free and accurate conversion. In this paper, theoretical and practical aspects of higher order incremental converters are discussed. The operating principles, topologies, specialized digital filter design methods, and circuit level issues are all addressed. It is shown how speed, resolution, and A/D complexity can be optimized for a given design, and how with some special digital filters improved speed/resolution ratio can be achieved. The theoretical results are verified by showing design examples and simulation results.

Theory and applications of incremental /spl Delta//spl Sigma/ converters

An 8-bit 80-Msample/s pipelined analog-to-digital converter (ADC) uses monolithic background calibration to reduce the nonlinearity caused by interstage gain errors Test results show that the ADC achieves a peak signal-to-noise-and-distortion ratio of 438 dB, a peak integral nonlinearity of 051 least significant bit (LSB), and a peak differential nonlinearity of 032 LSB with active background calibration It dissipates 268 mW from a 3 V supply and occupies 103 mm/sup 2/ in a single-poly 05 /spl mu/m CMOS technology

An 8-bit 80-Msample/s pipelined analog-to-digital converter with background calibration

A/D converters used in telemetry, instrumentation, and measurements require high accuracy, excellent linearity, and negligible DC offset, but need not be fast. A simple and robust instrumentation A/D converter, fabricated in a low-voltage 4-/spl mu/m CMOS technology, is described. The measured overall accuracy was 16 bits. Using a digital compensation for parasitic effects, both offset and nonlinearity were below 12 /spl mu/V. With analog compensation, the offset was 60 /spl mu/V and the nonlinearity below 15 /spl mu/V. These results indicate that even higher accuracy can be achieved using higher voltage technology.

P. Deval

Papers

A 16-bit low-voltage CMOS A/D converter