This paper presents 60-GHz wafer-scale transmit phased arrays with 64- and 256-elements spaced $\lambda $ /2 apart in the $x$ - and $y$ -directions, and occupying an area of 21.4 $\times $ 22 mm2 (471 mm2) and 41.4 $\times $ 42 mm2 (1740 mm2), respectively. The 64-element phased array is built as a complete reticle and includes 64 independent transmit channels with 5-b phase control, 3-b (9 dB) amplitude control, a saturated output power of 3 dBm at the antenna port, a 1–64 distribution network with redundant line amplifiers, and a high-efficiency on-chip antenna at each element. In addition, redundant serial digital interface and power strips, dual series metal–insulator–metal capacitors, and multiple RF inputs are employed for improved yield. The 256-element array uses the same phased-array blocks as the 64-element design, but is built using a subreticle stitching technique so as to result in a chip which is larger than the standard reticle size (22 $\times $ 22 mm2). The 64- and 256-element arrays result in a half-power beamwidth of 12° and 6° in the $E$ - and $H$ -planes, a directivity of 23 and 29 dB, respectively, and scan to ±55° in the $E$ - and $H$ -planes with near-ideal patterns and a cross-polarization level of lesser than −30 dB. The measured equivalent isotropically radiated power (EIRP) of the 64-element array is 38 dBm at 62 GHz with a 3-dB bandwidth of 61–63 GHz, while that of the 256-element array is 45 dBm at 61 GHz with a 3-dB beamwidth of 58–64 GHz. A 1–4-Gb/s communication system is also demonstrated using the 64-element phased array up to ±45° scan angles, and at 4-, 30-, and 100-m ranges. To the best of our knowledge, this paper represents the first demonstration of large size (64- and 256-element) phased-array transmitters on a single wafer.

60-GHz 64- and 256-Elements Wafer-Scale Phased-Array Transmitters Using Full-Reticle and Subreticle Stitching Techniques

This work introduces a 2-D phased array architecture that is suitable for high power radiation at mm-Wave and Terahertz frequencies. We address the challenge of signal generation above the cut-off frequency of transistors by presenting a radiation method based on the collective performance of a large number of synchronized sources. As theory shows, both frequency locking/tuning and beam steering can be independently achieved by manipulating the local coupling between the nearest neighbors. This control method results in a dynamical network that is insensitive to array dimensions and is scalable to the point that can achieve a level of output power and spectral purity beyond the reach of conventional sources. To demonstrate the concept, we implement a 4 $\times$ 4 version of this phased array at 340 GHz using a 65 nm bulk CMOS process. The paper presents the design and implementation of the oscillators, couplings and the integrated antennas. The measured results at 338 GHz reveal a peak equivalent isotropically radiated power (EIRP) of +17.1 dBm and a phase noise of -93 dBc/Hz at the 1 MHz offset frequency. This chip presents the first fully integrated terahertz phased array on silicon. Furthermore, the output power is higher than any lens-less silicon-based source above 200 GHz and the phase noise is lower than all silicon radiating sources above 100 GHz.

A High-Power and Scalable 2-D Phased Array for Terahertz CMOS Integrated Systems

A 94-GHz phased-array transceiver IC for frequency modulated continuous wave (FMCW) radar with four transmitters, four receivers, and integrated LO generation has been designed and fabricated in a 130-nm SiGe BiCMOS technology, and integrated into an antenna-in-package module. The transceiver, targeting gesture recognition applications for mobile devices, has been designed using phased-array techniques to reduce the total DC power while still maintaining the required link budget for FMCW operation. The complete array achieves state-of-the-art for W-band per-element power consumption of 106 mW per TX element and 91 mW per RX element, and measurements indicate a per-element output power of 6.4 dBm and single-sideband noise figure of 12.5 dB at 94 GHz. The array is able to achieve a beam steering range of ±20° while maintaining at least 3 dB main lobe to side lobe levels. The complete chip-antenna module has been tested to characterize basic FMCW radar functionality. Initial radar experiments suggest a sub-5-cm range resolution is possible with 3.68 GHz RF sweep bandwidth, which is in line with theoretical predictions.

https://ieeexplore.ieee.org/ielaam/4/7907348/7890392-aam.pdf

A 94-GHz 4TX–4RX Phased-Array FMCW Radar Transceiver With Antenna-in-Package

For decades, the principal role of microwave engineering techniques in the submillimeter (submm)-wave, or terahertz (THz), regime, spanning about 300 GHz-3 THz, has been to optimize the performance of components and systems used in molecular spectroscopy measurements for astronomy, earth science, and plasma diagnostics [1]. THz applications beyond spectroscopy have been much slower to develop. Ultrahigh bandwidth communication at THz frequencies may have the most powerful market forces to support it, but no systems have been deployed beyond the prototype stage, likely because of the unavailability of commercial submm-wave components, challenges with integrating them with existing communications hardware, and the often severe atmospheric attenuation.

Submillimeter-Wave Radar: Solid-State System Design and Applications

We propose a nonlinear device model and a systematic methodology to generate maximum power at any desired harmonic. The proposed power optimization technique is based on the Volterra-Wiener theory of nonlinear systems. By manipulating the device nonlinearity and optimizing the embedding network, optimum conditions for harmonic power generation are provided. Using this theory, a 920–944-GHz frequency quadrupler is designed in a 130-nm SiGe:C process. The circuit achieves the peak output power of −17.3 and −10 dBm of effective isotropic radiated power and consumes 5.7 mW of dc power. To the best of our knowledge, this circuit demonstrates the highest generated power among Si/SiGe-based sources at this frequency range.

A 0.92-THz SiGe Power Radiator Based on a Nonlinear Theory for Harmonic Generation

This paper presents a fully-integrated 3D image radar engine utilizing beamforming for electrical scanning and precise ranging technique for distance measurement. Four transmitters and four receivers form a sensor frontend with phase shifters and power combiners adjusting the beam direction. A built-in 31.3 GHz clock source and a frequency tripler provide both RF carrier and counting clocks for the distance measurement. Flip-chip technique with low-temperature co-fired ceramic (LTCC) antenna design creates a miniature module as small as 6.5 × 4.4 × 0.8 cm
 3
. Designed and fabricated in 65 nm CMOS technology, the transceiver array chip dissipates 960 mW from a 1.2-V supply and occupies chip area of 3.6 × 2.1 mm 2. This prototype achieves ±28° scanning range, 2-m maximum distance, and 1 mm depth resolution.

A 94 GHz 3D Image Radar Engine With 4TX/4RX Beamforming Scan Technique in 65 nm CMOS Technology

This paper presents two fully integrated binary phase-shift keying (BPSK) and quadrature phase-shift keying (QPSK) transceivers operating at W-band [carrier frequency = 84 GHz (BPSK), and 87 GHz (QPSK)]. Including RF front-end, Costas-loop-based carrier and data recovery, and antenna assembly technique, the BPSK transceiver prototype achieves a 2.5-Gb/s data link with BER <; 10-9 while consuming 202 mW (Tx) and 125 mW (Rx) from a 1.2-V supply. The QPSK TRx achieves a 2.5-Gb/s data link with BER <; 10-11 while consuming 212 mW (Tx) and 166 mW (Rx) from a 1.2-V supply. Both cases are measured with link distance of 1 m and antenna gain of 24 dBi.

$W$ -Band BPSK and QPSK Transceivers With Costas-Loop Carrier Recovery in 65-nm CMOS Technology

Millimeter-Wave and sub-THz imaging sensors have been demonstrated in CMOS technology recently. Mechanical scanners are still required to capture the whole image, making the systems bulky and costly. The limited resolution of the third-dimension (z-direction) also leads to a vague 3D picture. Other 2D solutions need not only focal lens, but large chip area to accommodate more pixels. This paper presents a 94GHz 3D image radar with electronic scanning. Using a 4TX/4RX beamforming technique and a modulated time-of-flight (ToF) algorithm, this prototype achieves ±28° scanning range, 2m maximum distance, and 1mm depth resolution with 960mW of power.

A 94GHz 3D-image radar engine with 4TX/4RX beamforming scan technique in 65nm CMOS

In recent years, the explosive growth of handheld smart devices has demanded increasing network capacity and higher data-rate. With around 1GHz bandwidth in the 5GHz UNII frequency band, 802.11ac offers great flexibility in utilizing a wider signal bandwidth and more complex modulation scheme to achieve the PHY rate up to 1.733Gb/s with VHT160 2×2 MIMO. The increased signal bandwidth from 80MHz (Stage1) to 160MHz (Stage2) poses stringent design challenges for radio transceivers, such as tighter frequency synthesizer phase-noise requirement for better EVM floor, techniques of using integrated high-power PAs for achieving 160MHz operation, and overcoming the effect of LPF 3dB-corner-mismatch-induced Frequency-Dependent IQ imbalance (FD-IQ) [1] due to finite OP-Amp Gain-BW product and submicron process gradient effect. This paper describes a monolithic MIMO 802.11ac Stage-2 Wi-Fi SoC chip with integrated dual-band PA's, LNA's, and T/R switches.

7.1 An 802.11ac dual-band reconfigurable transceiver supporting up to four VHT80 spatial streams with 116fs rms -jitter frequency synthesizer and integrated LNA/PA delivering 256QAM 19dBm per stream achieving 1.733Gb/s PHY rate

This work presents a novel 77GHz automotive radar providing detection distance and angle up to 100m and ±8°, respectively. Using a 1TX/4RX array, this radar system employs various mmWave techniques to fulfill the expected SNR.

Pang-Ning Chen

Papers

A 94 GHz 3D Image Radar Engine With 4TX/4RX Beamforming Scan Technique in 65 nm CMOS Technology

$W$ -Band BPSK and QPSK Transceivers With Costas-Loop Carrier Recovery in 65-nm CMOS Technology

A 94GHz 3D-image radar engine with 4TX/4RX beamforming scan technique in 65nm CMOS

7.1 An 802.11ac dual-band reconfigurable transceiver supporting up to four VHT80 spatial streams with 116fs rms -jitter frequency synthesizer and integrated LNA/PA delivering 256QAM 19dBm per stream achieving 1.733Gb/s PHY rate

A Fully-Integrated 77GHz phase-array radar system with 1TX/4RX frontend and digital beamforming technique