The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures. This survey presents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. First, research relating to the actual network design is reviewed. Then system level design and modeling are discussed. We also evaluate performance analysis techniques. The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.

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A survey of research and practices of Network-on-chip

A method for design optimization using logical and physical information is provided. In one embodiment, a method for design optimization using logical and physical information, includes receiving a behavioral description of an integrated circuit or a portion of an integrated circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements in accordance with a second cost function, in which the optimizing placement of the circuit elements and the optimizing logic of the circuit elements are performed concurrently. The method can further include optimizing routing in accordance with a third cost function, in which the optimizing routing, the optimizing placement of the circuit elements, and the optimizing logic of the circuit elements are performed concurrently.

Method for design optimization using logical and physical information

We introduce PHANTOM [1] a new secure processor that obfuscates its memory access trace. To an adversary who can observe the processor's output pins, all memory access traces are computationally indistinguishable (a property known as obliviousness). We achieve obliviousness through a cryptographic construct known as Oblivious RAM or ORAM. We first improve an existing ORAM algorithm and construct an empirical model for its trusted storage requirement. We then present PHANTOM, an oblivious processor whose novel memory controller aggressively exploits DRAM bank parallelism to reduce ORAM access latency and scales well to a large number of memory channels. Finally, we build a complete hardware implementation of PHANTOM on a commercially available FPGA-based server, and through detailed experiments show that PHANTOM is efficient in both area and performance. Accessing 4KB of data from a 1GB ORAM takes 26.2us (13.5us for the data to be available), a 32x slowdown over accessing 4KB from regular memory, while SQLite queries on a population database see 1.2-6x slowdown. PHANTOM is the first demonstration of a practical, oblivious processor and can provide strong confidentiality guarantees when offloading computation to the cloud.

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PHANTOM: practical oblivious computation in a secure processor

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Challenges for Nanoscale MOSFETs and Emerging Nanoelectronics

A semiconductor device includes a substrate and a number of diffusion regions defined within the substrate. The diffusion regions are separated from each other by a non-active region of the substrate. The semiconductor device includes a number of linear gate electrode tracks defined to extend over the substrate in a single common direction. Each linear gate electrode track is defined by one or more linear gate electrode segments. Each linear gate electrode track that extends over both a diffusion region and a non-active region of the substrate is defined to minimize a separation distance between ends of adjacent linear gate electrode segments within the linear gate electrode track, while ensuring adequate electrical isolation between the adjacent linear gate electrode segments.

Dynamic array architecture

An automated logic circuit design system uses a common database to store design data at different states of the design process, including data-flow graphs, netlists and layout descriptions. In this way, the need to translate circuit descriptions between tools is eliminated, thus leading to increased speed, flexibility and integration. The common database includes entities, models, cells, pins, busses and nets. The data-flow graphs are stored as graphs, the nodes in a graph as cells, and the edges as busses. Physical design data is available by storing the cells in a model in a KD tree. This allows queries on cells in the netlist located in the layout within arbitrary areas.

Method for storing multiple levels of design data in a common database

An automated method for designing an integrated circuit layout with a computer, based upon an electronic circuit description and upon a selected plurality of cells from a cell library, comprising the steps of: (a) assigning each of the cells to one of a plurality of buckets designated on the integrated circuit layout, each of the cells being connected to one of the other cells; (b) performing global routing to connect at least some of the selected cells of step (a) together such that global routes are formed to provide net topology information; (c) performing track routing which sets the position of each of the global routes; (d) performing detailed placement such that the positions of all selected cells are fixed within each of the buckets designated on the integrated circuit layout; and (e) performing detailed routing such that detailed routes are formed to complete the integrated circuit layout.

Method of designing a constraint-driven integrated circuit layout

Advancing technology drives design technology and thus design automation (EDA). How to model interconnect, how to handle degradation of signal integrity and increasing power density are changing now, and have led to integrating logic and layout synthesis. Aggressive gate sizing to control timing has become part of any modern back-end. From 0.13 /spl mu/ and down, chips will be more susceptive to breakdown during fabrication (antenna effect) or to wear out over time (electromigration) and dealing with these issues will require careful planning. More integration of fast and accurate analysis with a complete design flow (chip planning, synthesis, placement and routing) will be needed, and still, advancing complexity will affect design and verification. Using hundreds of millions of devices effectively will be possible only by reusing pre-designed intellectual property (IP) effectively and by addressing system-level issues in EDA. In the long term only more radical changes will keep us on Moore's track, changes that ultimately will have us depart from the two/sup +/-dimensional confinement and lead to multiple active layers, and changes that will affect deeply the face of EDA altogether.

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Design automation for deepsubmicron: present and future

It is a great pleasure to welcome you to the 49th annual edition of the Design Automation Conference, appropriately held in beautiful San Francisco. Since 1964, which is even before the beginning of Moore's law, DAC is the place where electronic systems design meets automation. In his keynote on Thursday, legendary professor Dave Liu will highlight the impact that DAC has had - and continues to have - in shaping our lives and the entire electronics industry. Without exaggeration, DAC is the premier place where thousands of professionals from all over the world converge to exchange ideas, sharpen skills and do business. And we will have a jolly good time doing all that. At the end of each day, join us for a reception to unwind while enjoying a view of the San Francisco skyline.

The 49th DAC in San Francisco is a true 'design rush' with hundreds of presentations, exhibitors, tutorials, panels and much more. The program is carefully designed to maximize personal interaction at all levels. We've reshaped the format of the technical presentations into concise 15-minute slots, with a poster session afterwards for in-depth face-to-face discussions. This year we had a significant increase in paper submissions. DAC's meticulous review process ensures that only the very best and most novel work is published at DAC. Domain experts from across the globe worked hard and entered a record 4,000 paper reviews, providing constructive feedback to future generations of EDA professionals.

Continuing on the interactive theme, our new 'Work-In-Progress' session intercepts and reshapes ideas before they are codified in a formal paper. At the session, DAC allows you to interact to shape the advanced research. Similarly our immensely popular 'Wild and Crazy Ideas' session provides food for thought in unexpected directions.

Proceedings of the 49th Annual Design Automation Conference

This paper introduces a special case of the floorplanning problem for optimizing neural networks to run on a wafer-scale computing engine. From a compute perspective, neural networks can be represented by a deeply layered structure of compute kernels. During the training of a neural network, gradient descent is used to determine the weight factors. Each layer then uses a local weight tensor to transform "activations" and "gradients" that are shared among connected kernels according to the topology of the network. This process is computationally intensive and requires high memory and communication bandwidth. Cerebras has developed a novel computer system designed for this work that is powered by a 21.5cm by 21.5cm wafer-scale processor with 400,000 programmable compute cores. It is structured as a regular array of 633 by 633 processing elements, each with its own local high bandwidth SRAM memory and direct high bandwidth connection to its neighboring cores. In addition to supporting traditional execution models for neural network training and inference, this engine has a unique capability to compile and compute every layer of a complete neural network simultaneously. Mapping a neural network in this fashion onto Cerebras' Wafer-Scale Engine (WSE) is reminiscent of the traditional floorplanning problem in physical design. A kernel ends up as a rectangle of x by y compute elements. These are the flexible blocks that need to be placed to optimize performance. This paper describes an ISPD 2020 challenge to develop algorithms and heuristics that produce compiled neural networks that achieve the highest possible performance on the Cerebras WSE.

Patrick Groeneveld

Papers

Method for storing multiple levels of design data in a common database

Method of designing a constraint-driven integrated circuit layout

Design automation for deepsubmicron: present and future

Proceedings of the 49th Annual Design Automation Conference

ISPD 2020 Physical Mapping of Neural Networks on a Wafer-Scale Deep Learning Accelerator