The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large. This led to the replacement of SiO2 by a physically thicker layer of a higher dielectric constant or ‘high-K’ oxide such as hafnium oxide. Intensive research was carried out to develop these oxides into high quality electronic materials. In addition, the incorporation of Ge in the CMOS transistor structure has been employed to enable higher carrier mobility and performance. This review covers both scientific and technological issues related to the high-K gate stack – the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging to achieve the thinnest oxide thicknesses. The high K oxides were implemented in conjunction with a replacement of polycrystalline Si gate electrodes with metal gates. The strong metallurgical interactions between the gate electrodes and the HfO2 which resulted an unstable gate threshold voltage resulted in the use of the lower temperature ‘gate last’ process flow, in addition to the standard ‘gate first’ approach. Work function control by metal gate electrodes and by oxide dipole layers is discussed. The problems associated with high K oxides on Ge channels are also discussed.

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High-K materials and metal gates for CMOS applications

Two different growth modes of large-area hexagonal boron nitride (h-BN) film, a conventional chemical vapor deposition (CVD) growth mode and a high-pressure CVD growth mode, were compared as a function of the precursor partial pressure. Conventional self-limited CVD growth was obtained below a critical partial pressure of the borazine precursor, whereas a thick h-BN layer (thicker than a critical thickness of 10 nm) was grown beyond a critical partial pressure. An interesting coincidence of a critical thickness of 10 nm was identified in both the CVD growth behavior and in the breakdown electric field strength and leakage current mechanism, indicating that the electrical properties of the CVD h-BN film depended significantly on the film growth mode and the resultant film quality.

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Synthesis and Characterization of Hexagonal Boron Nitride as a Gate Dielectric

3D monolithic integration of logic and memory has been the most sought after solution to surpass the Von Neumann bottleneck, for which a low-temperature processed material system becomes inevitable. Two-dimensional materials, with their excellent electrical properties and low thermal budget are potential candidates. Here, we demonstrate a low-temperature hybrid co-integration of one-transistor-one-resistor memory cell, comprising a surface functionalized 2D WSe2 p-FET, with a solution-processed WSe2 Resistive Random Access Memory. The employed plasma oxidation technique results in a low Schottky barrier height of 25 meV with a mobility of 230 cm2 V−1 s−1, leading to a 100x performance enhanced WSe2 p-FET, while the defective WSe2 Resistive Random Access Memory exhibits a switching energy of 2.6 pJ per bit. Furthermore, guided by our device-circuit modelling, we propose vertically stacked channel FETs for high-density sub-0.01 μm2 memory cells, offering a new beyond-Si solution to enable 3-D embedded memories for future computing systems. Designing efficient, scalable and low-thermal-budget 2D Materials for 3D integration remains a challenge. Here, the authors report the development of a hybrid-(solution-processed-exfoliated) integration of 2D Material based 1T1R which uses a multilayer WSe2 p-FET and a multilayer printed WSe2 RRAM.

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All WSe2 1T1R resistive RAM cell for future monolithic 3D embedded memory integration.

We propose to create lateral heterojunctions in two-dimensional materials based on nonlocal manipulations of the Coulomb interaction using structured dielectric environments. By means of ab initio calculations for MoS2 as well as generic semiconductor models, we show that the Coulomb interaction-induced self-energy corrections in real space are sufficiently nonlocal to be manipulated externally, but still local enough to induce spatially sharp interfaces within a single homogeneous monolayer to form heterojunctions. We find a type-II heterojunction band scheme promoted by a laterally structured dielectric environment, which exhibits a sharp band gap crossover within less than 5 unit cells.

Two-Dimensional Heterojunctions from Nonlocal Manipulations of the Interactions

Miniaturization of optoelectronic devices offers tremendous performance gain. As the volume of photoactive material decreases, optoelectronic performance improves, including the operation speed, the signal-to-noise ratio, and the internal quantum efficiency. Over the past decades, researchers have managed to reduce the volume of photoactive materials in solar cells and photodetectors by orders of magnitude. However, two issues arise when one continues to thin down the photoactive layers to the nanometer scale (for example, <50 nm). First, light-matter interaction becomes weak, resulting in incomplete photon absorption and low quantum efficiency. Second, it is difficult to obtain ultrathin materials with single-crystalline quality. We introduce a method to overcome these two challenges simultaneously. It uses conventional bulk semiconductor wafers, such as Si, Ge, and GaAs, to realize single-crystalline films on foreign substrates that are designed for enhanced light-matter interaction. We use a high-yield and high-throughput method to demonstrate nanometer-thin photodetectors with significantly enhanced light absorption based on nanocavity interference mechanism. These single-crystalline nanomembrane photodetectors also exhibit unique optoelectronic properties, such as the strong field effect and spectral selectivity.

https://advances.sciencemag.org/content/advances/3/7/e1602783.full.pdf

Single-crystalline germanium nanomembrane photodetectors on foreign nanocavities.

A novel design for a silicon-integrated avalanche photodiode (APD) capable of high internal gain (>16,000) is presented. The APD was fabricated in an unmodified, commercial high-volume, high-performance (300 GHz ${f}_{T}/{f}_{\text {MAX}}$ ) silicon-germanium (SiGe) BiCMOS technology. The APD’s high gain is partially attributed to the enhanced lateral carrier mobility of its strained SiGe anode, and the low sheet resistance of its cathode contact. These design aspects lower parasitic resistance and improve junction electric field uniformity, increasing maximum gain. For applications not requiring maximum device speed, a time-resolved overall responsivity of 4.2 A/W is demonstrated, with a photocurrent pulse fall time (90%/10%) of 46 ns at 1066 nm. Alternatively, for applications requiring faster speed, the device can be biased to 0.16 A/W with a fall time of 2.5 ns, or 0.07 A/W with a fall time of 0.8 ns.

Zero-Process-Change SiGe Heterojunction Avalanche Photodiode for High-Speed, High-Gain Detection Near the Silicon Band Edge

This article presents an experimental study of single-event transients (SETs) induced by pulsed X-rays in SiGe heterojunction bipolar transistors (HBTs). Device-level transient data and circuit-level upset data from pulsed X-rays are analyzed and compared to those of heavy-ions. 3-D TCAD modeling is utilized to understand the source of the differences in the transients. The transient peak from the ion-shunt effect is not present in pulsed X-ray transients due to its large spot size and slow pulse transition, both of which lead to lower peak carrier densities. The diffusion “tail,” typically present in transients measured from SiGe HBTs, also differs between the two sources. The charge collection of X-ray has a linear correlation with surface linear energy transfer (LET) across the photon energies of 8–12 keV. For a similar surface LET, the impinging heavy-ion pushes the subcollector-substrate junction boundaries of the SiGe HBT deeper, resulting in higher charge collection. Single-event upset (SEU) screening of shift-registers shows that X-ray can detect device sensitive nodes smaller than the beam.

Patrick S. Goley

Papers

Zero-Process-Change SiGe Heterojunction Avalanche Photodiode for High-Speed, High-Gain Detection Near the Silicon Band Edge

Single-Event Transients in SiGe HBTs Induced by Pulsed X-Ray Microbeam