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Per Ranstad

Researcher at Alstom

Publications -  45
Citations -  685

Per Ranstad is an academic researcher from Alstom. The author has contributed to research in topics: Power semiconductor device & MOSFET. The author has an hindex of 14, co-authored 43 publications receiving 621 citations. Previous affiliations of Per Ranstad include General Electric & Brown, Boveri & Cie.

Papers
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Journal ArticleDOI

Automated Design of a High-Power High-Frequency LCC Resonant Converter for Electrostatic Precipitators

TL;DR: This work presents an automated design procedure for series parallel resonant converters employed in electrostatic precipitator (ESP) power supplies, which reduces the designer effort significantly.
Journal ArticleDOI

On Dynamic Effects Influencing IGBT Losses in Soft-Switching Converters

TL;DR: In this paper, two different dynamic effects influencing the insulated gate bipolar transistor (IGBT) losses in soft-switching converters are demonstrated, and it is shown by experiments that the on-state losses depend on the operating frequency.
Journal ArticleDOI

An Experimental Evaluation of SiC Switches in Soft-Switching Converters

TL;DR: In this paper, the authors compared several types of SiC transistors to a state-of-the-art 1200-V Si IGBT and found that the SiC-transistors showed no signs of dynamic conduction losses in the studied frequency range.
Patent

Voltage source converter (VSC) with neutral-point-clamped (NPC) topology and method for operating such voltage source converter

TL;DR: A Voltage Source Converter (VSC) with Neutral-Point-Clamped (NPC) topology with one or more phases, comprises an intermediate DC circuit having at least a first and a second capacitance connected in series between a positive terminal and a negative terminal, providing a central tap terminal between both capacitances, and at least one sub-circuit for generating one phase of an alternating voltage, each subcircuit comprising an AC terminal for supplying a pulsed voltage as discussed by the authors.
Proceedings ArticleDOI

Analysis of parasitic elements of SiC power modules with special emphasis on reliability issues

TL;DR: In this article, a half-bridge SiC MOSFET has been modeled and the parasitic elements have been extracted, and an analysis of the impact of these parasitic elements on the gate-source voltage on the chip has been performed for both low switching speeds and high switching speeds.