Showing papers by "Peter A. Beerel published in 1998"

The design and verification of a high-performance low-control-overhead asynchronous differential equation solver

Abstract: This paper describes the design and verification of a high-performance asynchronous differential equation solver benchmark circuit The design has low-control-overhead which allows its average-case speed (tested at 22/spl deg/C and 33 V) to be 48% faster than any comparable synchronous design (designed to operate at 100/spl deg/C and 3 V for the slow process corner) The techniques to reduce completion sensing overhead and hide control overhead at the circuit, architectural, and protocol levels are discussed In addition, symbolic model checking techniques are described that were used to gain higher confidence in the correctness of the timed distributed control

Efficient state classification of finite-state Markov chains

Abstract: This paper presents an efficient method for state classification of finite-state Markov chains using binary-decision diagram-based symbolic techniques. The method exploits the fundamental properties of a Markov chain and classifies the state space by iteratively applying reachability analysis. We compare our method with the state-of-the-art technique, which requires the transitive closure of the transition relation of a Markov chain. Experiments in over a dozen synchronous and asynchronous systems and queueing networks demonstrate that our method dramatically reduces the CPU time needed and solves much larger problems because of the reduced memory requirements.

Covering conditions and algorithms for the synthesis of speed-independent circuits

Abstract: This paper presents theory and algorithms for the synthesis of standard C-implementations of speed-independent circuits. These implementations are block-level circuits which may consist of atomic gates to perform complex functions in order to ensure hazard freedom. First, we present Boolean covering conditions that guarantee that the standard C-implementations operate correctly. Then, we present two algorithms that produce optimal solutions to the covering problem. The first algorithm is always applicable, but does not complete on large circuits. The second algorithm, motivated by our observation that our covering problem can often be solved with a single cube, finds the optimal single-cube solution when such a solution exists. When applicable, the second algorithm is dramatically more efficient than the first, more general algorithm. We present results for benchmark specifications which indicate that our single-cube algorithm is applicable on most benchmark circuits and reduces run times by over an order of magnitude. The block-level circuits generated by our algorithms are a good starting point for tools that perform technology mapping to obtain gate-level speed-independent circuits.

Efficient state classification of finite state Markov chains

Abstract: This paper presents an efficient method for state classification of finite state Markov chains using BDD-based symbolic techniques. The method exploits the fundamental properties of a Markov chain and classifies the state space by iteratively applying reachability analysis. We compare our method with the current state-of-the-art technique which requires the computation of the transitive closure of the transition relation of a Markov chain. Experiments in over a dozen synchronous and asynchronous systems demonstrate that our method dramatically reduces the CPU time needed, and solves much larger problems because of reduced memory requiremen ts.

Average-case optimized technology mapping of one-hot domino circuits

Abstract: This paper presents a technology mapping technique for optimizing the average-case delay of asynchronous combinational circuits implemented using domino logic and one-hot encoded outputs. The technique minimizes the critical path for common input patterns at the possible expense of making less common critical paths longer. To demonstrate the application of this technique, we present a case study of a combinational length decoding block, an integral component of an Asynchronous Instruction Length Decoder (AILD) which can be used in Pentium(R) processors. The experimental results demonstrate that the average-case delay of our mapped circuits can be dramatically lower than the worst-case delay of the circuits obtained using conventional worst-case mapping techniques.

Don't care-based BDD minimization for embedded software

Abstract: This paper explores the use of don't cares in software synthesis for embedded systems. Embedded systems have extremely tight real-time and code/data size constraints, that make expensive optimizations desirable. We propose applying BDD minimization techniques in the presence of a don't care set to synthesize code for extended Finite State Machines from a BDD-based representation of the FSM transition function. The don't care set can be derived from local analysis (such as unused state codes or don't care inputs) as well as from external information (such as impossible input patterns). We show experimental results, discuss their implications, the interaction between BDD-based minimization and dynamic variable reordering, and propose directions for future work.

Checking combinational equivalence of speed-independent circuits

Abstract: We introduce the notion of combinational equivalence to relate two speed-independent asynchronous (sequential) circuits: a “golden” hazard-free circuit C_1 and a “target” circuit C_2 that can be derived from C_1 through only combinational decomposition and extraction. Both circuits are assumed to be networks of single-output basic gates; multiple output gates such as arbiters, toggles, and dual-rail function blocks are not considered. We say that the circuits are combinationally equivalent if the decomposition and extraction preserves the essential functionality of the combinational blocks in the circuit and does not introduce hazards. The paper‘s focus is the bottleneck of the verification procedure, checking whether C_2 is hazard-free. We show that C_2 is hazard-free if and only if all of its signals are monotonic and acknowledged . We then show how cubes that approximate sets of reachable circuit states can be used to give sufficient conditions for monotonicity and acknowledgement. These sufficient conditions are used to develop a verification technique for combinational equivalence that can be exponentially faster than applying traditional, more general verification techniques. This result can be useful for verifying logic synthesis and technology mapping procedures.

Computer engineering using innovative instructional technologies at the University of Southern California

Abstract: Our ultimate goal as university educators is to guide students through perhaps the most important stage of a life-long learning experience. The principal challenges associated with achieving this goal for computer engineering students are to• teach them the engineering fundamentals and specializations they need to successfully develop and integrate various software and hardware components into a complex product,• provide them with the underlying engineering ethics and economics as well as liberal arts exposure that will guide them to develop products beneficial to our society,• empower them with the oral and written communication skills needed to thrive in typical team-based engineering environments, and• impart to them a learning experience that is rewarding rather than frustrating by better teaching back-breaker concepts and by more finely interlacing lectures with hands-on lab experience.