P
Peter Jamieson
Researcher at Miami University
Publications - 61
Citations - 1356
Peter Jamieson is an academic researcher from Miami University. The author has contributed to research in topics: Field-programmable gate array & Simulated annealing. The author has an hindex of 12, co-authored 55 publications receiving 1251 citations. Previous affiliations of Peter Jamieson include Imperial College London & University of Toronto.
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Proceedings ArticleDOI
The VTR project: architecture and CAD for FPGAs from verilog to routing
Jonathan Rose,Jason Luu,Chi Wai Yu,Opal Densmore,Jeffrey Goeders,Andrew Somerville,Kenneth B. Kent,Peter Jamieson,Jason H. Anderson +8 more
TL;DR: The current status and new release of an ongoing effort to create a downstream full-implementation flow of Verilog to Routing is described, and the use of the new flow is illustrated by using it to help architect a floating-point unit in an FPGA, and compared with a prior, much longer effort.
Journal ArticleDOI
VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling
Jason Luu,Ian Kuon,Peter Jamieson,Ted Campbell,Andy Ye,Wei Mark Fang,Kenneth B. Kent,Jonathan Rose +7 more
TL;DR: A new version of the VPR toolset is described and illustrated that supports a broad range of single-driver routing architectures, and provides optimized electrical models for a wide range of architectures in different process technologies, including a range of area-delay trade-offs for each single architecture.
Proceedings ArticleDOI
VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling
TL;DR: A new version of the VPR toolset is described that supports a broad range of single-driver routing architectures and provides optimized electrical models of a wide range of architectures in different process technologies, including a range of area-delay tradeoffs for each single architecture.
Proceedings ArticleDOI
Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research
TL;DR: Odin II is a framework for Verilog Hardware Description Language (HDL) synthesis that allows researchers to investigate approaches/improvements to different phases of HDL elaboration that have not been previously possible and can be used by ASIC and FPGA researchers for more than basic synthesis.
Proceedings ArticleDOI
An energy and power consumption analysis of FPGA routing architectures
TL;DR: The results show that uni-directional routing architecture, in all but one case, is the most energy efficient choice both in the traditional FPGA domain and the mobile domain where clock frequencies are fixed.