P
Piyali Datta
Researcher at University of Calcutta
Publications - 35
Citations - 75
Piyali Datta is an academic researcher from University of Calcutta. The author has contributed to research in topics: Biochip & Simple polygon. The author has an hindex of 4, co-authored 33 publications receiving 65 citations. Previous affiliations of Piyali Datta include Heritage Institute of Technology.
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Proceedings ArticleDOI
A technology shift towards triangular electrodes from square electrodes in design of Digital Microfluidic Biochip
TL;DR: In this paper, the authors proposed a design using equilateral triangular electrodes instead of square electrodes, maintaining all the constraints required to ensure safe droplet movement and other modular operations, while improvement of the mixing operation is the key design issue.
Journal ArticleDOI
Fluid-level synthesis unifying reliability, contamination avoidance, and capacity-wastage-aware washing for droplet-based microfluidic biochips
TL;DR: A complete fluid-level synthesis considering all the essential goals together instead of dealing with them in isolation is proposed effectively handles the trade-off scenarios and provides flexibility to the designer to decide the threshold of the individual optimisation objective leading to the construction of a good-quality solution as a whole.
Proceedings ArticleDOI
Design Optimization at the Fluid-Level Synthesis for Safe and Low-Cost Droplet-Based Microfluidic Biochips
TL;DR: A fluid-level design for DMFBs is proposed that is capable of handling reliability and also free from cross contamination, and a graph model has been used to tackle them.
Proceedings ArticleDOI
A Capacity-Aware Wash Optimization for Contamination Removal in Programmable Microfluidic Biochip Devices
TL;DR: A wash optimization model is proposed that aims to remove all the contaminations while minimizing washing time and total capacity wastage and has been evaluated considering a number of baseline methods and the previous works.
Book ChapterDOI
A 2D Guard Zone Computation Algorithm for Reassignment of Subcircuits to Minimize the Overall Chip Area
TL;DR: The algorithm developed is proved to report a preferred guard zone of the given simple polygon excluding all the intersections, if any, and is output sensitive in nature that depends on the value of δ i.