Increasing data rates, spectrum efficiency, and energy efficiency have been driving major advances in the design and hardware integration of RF communication networks. In order to meet the data rate and efficiency metrics, fifth-generation (5G) networks have emerged as a follow-on to 4G and projected to have $100\times $ higher wireless date rates and $100\times $ lower latency than those with current 4G networks. Major challenges arise in the packaging of radio frequency front-end modules because of the stringent low signal-loss requirements in the millimeter-wave frequency bands, and precision-impedance designs with smaller footprints and thickness. Heterogeneous integration in 3-D ultrathin packages with higher component densities and performance than with the existing 2-D packages is needed to realize such 5G systems. This article reviews the key building blocks of 5G systems and the underlying advances in packaging technologies to realize them.

A Review of 5G Front-End Systems Package Integration

A method of manufacturing a semiconductor package includes: coupling a semiconductor die to a protection layer; forming a first redistribution layer over the semiconductor die, wherein the first redistribution layer includes a first conductive plate and a first dielectric material laterally surrounding the first conductive plate; forming a recess in the first redistribution layer, wherein the recess is over the first conductive plate and defined by the first dielectric material; depositing an insulating film in the recess with a second dielectric material of a dielectric constant greater than a dielectric constant of the first dielectric material; and forming a second redistribution layer including a second conductive plate over the insulating film. The insulating film electrically isolates the first conductive plate from the second conductive plate, and one of the first conductive plate and the second conductive plate is configured to radiate or receive electromagnetic wave.

Semiconductor package device with integrated inductor and manufacturing method thereof

In accordance with some embodiments, a package structure includes an RFIC chip. an insulating encapsulation, a redistribution circuit structure, an antenna and a microwave director. The insulating encapsulation encapsulates the RFIC chip. The redistribution circuit structure is disposed on the insulating encapsulation and electrically connected to the RFIC chip. The antenna is disposed on the insulating encapsulation and electrically connected to the RFIC chip through the redistribution circuit structure. The antenna is located between the microwave director and the RFIC chip. The microwave director has a microwave directivity enhancement surface located at a propagating path of a microwave received or generated by the antenna.

Package structure, electronic device and method of fabricating package structure

In this work, a substrate integrated 3D solenoid inductor with an ultra-high quality factor (Q-factor) is demonstrated using the combination of Through Fused-silica Vias (TFVs) for low substrate loss and Copper (Cu) / Cobalt (Co) metaconductors for low conductor loss for millimeter wave (mmWave) applications. Especially, a Cu/Co metaconductor based 1 turn 3D solenoid inductor is integrated on a $300\ \mu\mathrm{m}$ thick fused-silica substrate with a small form factor of $170\ \mu\mathrm{m}\times 200\ \mu\mathrm{m}$ . The Cu/Co inductor shows a peak Q-factor of 204 while a solid Cu counterpart does a Q-factor of 88.9 at 28.4 GHz, showing 130% Q-factor improvement. Modeling and optimization of the inductors has been performed using a lumped element circuit model and High Frequency Structure Simulator (HFSS) simulation. Design, fabrication, and characterization of the inductors is detailed.

Ultra-High Q-factor Through Fused-silica Via (TFV) Integrated 3D Solenoid Inductor for Millimeter Wave Applications

A method of forming a semiconductor package structure (30b) includes providing a first wafer-level package structure having a die region surrounded by a scribe line region. The first wafer-level package structure includes a first encapsulating layer (108), a first redistribution layer (RDL) structure (120) formed on the first encapsulating layer, a first antenna element (130a) formed in the first RDL structure and corresponding to the die region, and a semiconductor die (100) in the first encapsulating layer and corresponding to the die region. A second wafer-level package structure is bonded onto the first RDL structure using a first adhesive layer (122'). The second wafer-level package structure includes a second encapsulating layer (124') attached to the first adhesive layer, and a second antenna element (130b) formed on the second encapsulating layer. The second antenna element and the first antenna element form a patch antenna (130) after the bonding of the second wafer-level package structure.

Semiconductor package with antenna and fabrication method thereof

A high performance 3D dipole antenna with metal thickness >100 μm for wide bandwidth and lateral radiation is realized on InFO package. 25 % wide fractional bandwidth, from 60 to 77 GHz, has been obtained. The beamforming capability of the antenna array system with 6 dBi gain is measured in a 40 nm CMOS RFIC co-designed system.

Fabrication and Characterization of Millimeter Wave 3D InFO Dipole Antenna Array Integrated with CMOS Front-end Circuits

A semiconductor package structure including an encapsulation body, an RFIC chip, a first antenna structure, and a second antenna structure is provided. The RFIC chip may be embedded in the encapsulation body. The first antenna structure may be disposed at a lateral side of the RFIC chip, electrically connected to the RFIC chip, and include a first conductor layer and a plurality of first patches opposite to the first conductor layer. The second antenna structure may be stacked on the RFIC chip, electrically connected to the RFIC chip, and include a second conductor layer and a plurality of second patches opposite to the second conductor layer. The first patches and the second patches are located at a surface of the encapsulation body. A first distance between the first conductor layer and the first patches is different from a second distance between the second conductor layer and the second patches.

Semiconductor package structure

A semiconductor device structure is provided. The semiconductor device structure includes a first device. The semiconductor device structure includes a conductive element over the first device. The semiconductor device structure includes a first conductive shielding layer between the first device and the conductive element. The first conductive shielding layer has openings, and a maximum width of the opening is less than a wavelength of an energy generated by the first device.

Semiconductor device structure and method for forming the same

A package structure in accordance with some embodiments may include an RFIC chip, a redistribution circuit structure, a backside redistribution circuit structure, an isolation film, a die attach film, and an insulating encapsulation. The redistribution circuit structure and the backside redistribution circuit structure are disposed at two opposite sides of the RFIC chip and electrically connected to the RFIC chip. The isolation film is disposed between the backside redistribution circuit structure and the RFIC chip. The die attach film is disposed between the RFIC chip and the isolation film. The insulating encapsulation encapsulates the RFIC chip and the isolation film between the redistribution circuit structure and the backside redistribution circuit structure. The isolation film may have a coefficient of thermal expansion lower than the insulating encapsulation and the die attach film.

Package structure and method of fabricating package structure

High Q-factor (quality factor) 3D solenoid inductor formed by RDL (redistribution layer) and copper via in the molding compound on InFO package was fabricated. The effect of the turns and cross sectional area on Q-factor is discussed. The 3D solenoid inductor with 3 turns achieves the Q-factor of 59 at 3GHz and 0.68× lower of resistance and 1.6× higher of Q-factor than 2D spiral inductor at the same inductance. The coupling between two closely placed inductors is also investigated and it is found that the coupling in orthogonal placement is 12 dB lower than that of in parallel placement. The sample was fabricated and measured. The measurement results agree with the simulation, indicating the feasibility of the 3D inductor on InFO package.

Pu Han-Ping

Papers

Fabrication and Characterization of Millimeter Wave 3D InFO Dipole Antenna Array Integrated with CMOS Front-end Circuits

Semiconductor package structure

Semiconductor device structure and method for forming the same

Package structure and method of fabricating package structure

High Q-factor 3D Solenoid Inductor on InFO Package for RF System Integration