International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

As industry moves towards many-core chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constraint, early-stage estimation of NoC power has become crucially important. ORION [29] was amongst the first NoC power models released, and has since been fairly widely used for early-stage power estimation of NoCs. However, when validated against recent NoC prototypes -- the Intel 80-core Teraflops chip and the Intel Scalable Communications Core (SCC) chip -- we saw significant deviation that can lead to erroneous NoC design choices. This prompted our development of ORION 2.0, an extensive enhancement of the original ORION models which includes completely new subcomponent power models, area models, as well as improved and updated technology models. Validation against the two Intel chips confirms a substantial improvement in accuracy over the original ORION. A case study with these power models plugged within the COSI-OCC NoC design space exploration tool [23] confirms the need for, and value of, accurate early-stage NoC power estimation. To ensure the longevity of ORION 2.0, we will be releasing it wrapped within a semi-automated flow that automatically updates its models as new technology files become available.

/pdf/orion-2-0-a-fast-and-accurate-noc-power-and-area-model-for-3pivncxvm6.pdf

ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

High-performance parallel computer architecture and systems have been improved at a phenomenal rate. In the meantime, VLSI computer-aided design (CAD) software for multibillion-transistor IC design has become increasingly complex and requires prohibitively high computational resources. Recent studies have shown that, numerous CAD problems, with their high computational complexity, can greatly benefit from the fast-increasing parallel computation capabilities. However, parallel programming imposes big challenges for CAD applications. Fully exploiting the computational power of emerging general-purpose and domain-specific multicore/many-core processor systems, calls for fundamental research and engineering practice across every stage of parallel CAD design, from algorithm exploration, programming models, design-time and run-time environment, to CAD applications, such as verification, optimization, and simulation. This journal special section will cover recent progress on parallel CAD research, including algorithm foundations, programming models, parallel architectural-specific optimization, and verification. More specifically, papers with in-depth and extensive coverage of the following topics will be considered, as well as other topics relevant to the design of parallel CAD algorithms and software tools. 1. Parallel algorithm design and specification for CAD applications 2. Parallel programming models and languages of particular use in CAD 3. Runtime support and performance optimization for CAD applications 4. Parallel architecture-specific design and optimization for CAD applications 5. Parallel program debugging and verification techniques particularly relevant for CAD The papers should be submitted via the Manuscript Central website and should adhere to standard ACM TODAES formatting requirements (http://todaes.acm.org/). The page count limit is 25.

Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems

3. FEOL Applications: Device Level 180 3.1. Shallow Trench Isolation (STI) CMP 180 3.2. Replacement Metal Gate CMP 184 3.3. Poly-Si CMP for FinFET Devices 186 4. MOL Applications: Contact Level 187 4.1. Tungsten CMP 187 5. BEOL Applications: Multilevel Interconnects 188 5.1. Copper Interconnect Technology 188 5.2. CMP Challenges in Cu Interconnects 189 5.2.1. Low-k and Ultralow-k Material Challenges 189 5.2.2. Integration Challenges 190 5.2.3. CMP Process Challenges 191 5.3. Copper Planarizarion Process 191 5.4. Ta/TaN Liner CMP Process 193 6. CMP Process-Induced Defects 194 6.1. Defects in FEOL CMP 194 6.2. Defects in MOL Tungsten CMP 195 6.3. Defects in Cu BEOL CMP 195 6.3.1. Corrosion of Copper 196 6.3.2. Scratches 196 6.3.3. Dishing, Erosion, and Trenching 196 6.3.4. Mechanical Damage 197 6.3.5. Other Defects 197 7. Models of CMP Processes 198 7.1. Models Based on Contact Mechanics 198 7.2. CMP Process Models 199 8. Alternative CMP Processes 200 9. Concluding Remarks 201 10. Acknowledgments 201 11. References 201

Chemical mechanical planarization: slurry chemistry, materials, and mechanisms.

With process scaling, leakage power reduction has become one of the most important design concerns. Multi-threshold techniques have been used to reduce runtime leakage power without sacrificing performance. In this paper, we propose small biases of transistor gate-length to further minimize power in a manufacturable manner. Unlike multi-V th techniques, gate-length biasing requires no additional masks and may be performed at any stage in the design process.Our results show that gate-length biasing effectively reduces leakage power by up to 25% with less than 4% delay penalty. We show the feasibility of the technique in terms of manufacturability and pin-compatibility for post-layout power optimization. We also show up to 54% reduction in leakage uncertainty due to inter-die process variation in circuits when biased gate-lengths, versus only unbiased one, are used. Circuits selectively biased show much less sensitivity to both intra and inter die variations.

/pdf/selective-gate-length-biasing-for-cost-effective-runtime-5fmheffa0h.pdf

Selective gate-length biasing for cost-effective runtime leakage control

Leakage power has become one of the most critical design concerns for the system-level chip designer. Multi-threshold techniques have been used to reduce runtime leakage power without sacrificing performance. In this paper we present an effective and scalable transistor-level V/sub th/ assignment approach and show leakage reduction over standard cell-level V/sub th/ assignment. The main disadvantage of transistor-level V/sub th/ assignment is increased cell library size and characterization effort. In comparison to previous approaches, our approach yields better solution quality, requires smaller cell library, is more accurate in considering the impact of V/sub th/ assignment on propagation delay, slew (transition delay) and capacitance, and is significantly faster.

/pdf/a-practical-transistor-level-dual-threshold-voltage-34gg3qwk2o.pdf

A practical transistor-level dual threshold voltage assignment methodology

Today's design-manufacturing interfaces have only minimal information exchange. Lack of information on either side leads to under-performance due to too much guardbanding, and increased mask cost and increased turnaround time due to over-correction. In this work we present techniques that simultaneously utilize design and manufacturing information to improve mask quality and reduce mask cost.

Joining the design and mask flows for better and cheaper masks

Leakage power has become one of the most critical design concerns for the system level chip designer. While lowered supplies (and consequently, lowered threshold voltage) and aggressive clock gating can achieve dynamic power reduction, these techniques increase the leakage power and, therefore, causes its share of total power to increase. Manufacturers face the additional challenge of leakage variability: Recent data indicate that the leakage of microprocessor chips from a single 180-nm wafer can vary by as much as 20/spl times/. Previously proposed techniques for leakage-power reduction include the use of multiple supply and gate threshold voltages, and the assignment of input values to inactive gates, such that leakage is minimized. The additional design space afforded by the biasing of device gate lengths to reduce chip leakage power and its variability is studied. It is well known that leakage power decreases exponentially and delay increases linearly with increasing gate length. Thus, it is possible to increase gate length only marginally to take advantage of the exponential leakage reduction, while impairing performance only linearly. From a design-flow standpoint, the use of only slight increases in gate length preserves both pin and layout compatibility; therefore, the authors' technique can be applied as a postlayout enhancement step. The authors apply gate-length biasing only to those devices that do not appear in critical paths, thus assuring zero or negligible degradation in chip performance. To highlight the value of the technique, the multithreshold voltage technique, which is widely used for leakage reduction, is first applied and then gate-length biasing is used to show further reduction in leakage. Experimental results show that gate-length biasing reduces leakage by 24%-38% for the most commonly used cells, while incurring delay penalties of under 10%. Selective gate-length biasing at the circuit level reduces circuit leakage by up to 30% with no delay penalty. Leakage variability is reduced significantly by up to 41%, which may lead to substantial improvements in the manufacturing yield and the product cost. The use of gate-length biasing for leakage optimization of cell instances is also assessed, in which: 1) not all timing arcs are timing critical and/or 2) the rise and fall transitions are not both timing critical at the same time.

/pdf/gate-length-biasing-for-runtime-leakage-control-31vbfc2lku.pdf

Gate-length biasing for runtime-leakage control

Starting at the 65 nm node, stress engineering to improve performance of transistors has been a major industry focus. An intrinsic stress source -shallow trench isolation -has not been fully utilized up to now for circuit performance improvement. In this paper, we present a new methodology that combines detailed placement and active-layer fill insertion to exploit STI stress for performance improvement. We perform process simulation of a production 65 nm STI technology to generate mobility and delay impact models for STI stress. Based on these models, we are able to perform STI stress-aware delay analysis of critical paths using SPICE. We then present our timing-driven optimization of STI stress in standard cell designs, using detailed placement perturbation to optimize PMOS performance and active-layer fill insertion to optimize NMOS performance. We assess our optimization on small designs implemented with a 65 nm production cell library and a standard synthesis, place and route flow. Our timing-driven optimization of STI stress impacts can improve clock frequency by between 7% to 11%. The frequency improvement through exploitation of STI stress comes at practically zero cost in terms of design area and wirelength.

/pdf/exploiting-sti-stress-for-performance-3c81xinzmj.pdf

Puneet Sharma

Papers

Selective gate-length biasing for cost-effective runtime leakage control

A practical transistor-level dual threshold voltage assignment methodology

Joining the design and mask flows for better and cheaper masks

Gate-length biasing for runtime-leakage control

Exploiting STI stress for performance