There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

The compelling demand for higher performance and lower power consumption in electronic systems is the main driving force of the electronics industry's quest for devices and/or architectures based on new materials. Here, we provide a review of electronic devices based on two-dimensional materials, outlining their potential as a technological option beyond scaled complementary metal-oxide-semiconductor switches. We focus on the performance limits and advantages of these materials and associated technologies, when exploited for both digital and analog applications, focusing on the main figures of merit needed to meet industry requirements. We also discuss the use of two-dimensional materials as an enabling factor for flexible electronics and provide our perspectives on future developments.

Electronics based on two-dimensional materials

Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

Tunnel field-effect transistors as energy-efficient electronic switches

Disclosed is a method for making graphene nanoribbons (GNRs) by controlled unzipping of structures such as carbon nanotubes (CNTs) by etching (e.g., argon plasma etching) of nanotubes partly embedded in a polymer film. The GNRs have smooth edges and a narrow width distribution (2-20 nm). Raman spectroscopy and electrical transport measurements reveal the high quality of the GNRs. Such a method of unzipping CNTs with well-defined structures in an array will allow the production of GNRs with controlled widths, edge structures, placement and alignment in a scalable fashion for device integration. GNRs may be formed from nanostructures in a controlled array to form arrays of parallel or overlapping structures. Also disclosed is a method in which the CNTs are in a predetermined pattern that is carried over and transferred to a substrate for forming into a semiconductor device.

Narrow graphene nanoribbons from carbon nanotubes

The celebrated electronic properties of graphene(1,2) have opened the way for materials just one atom thick(3) to be used in the post-silicon electronic era(4). An important milestone was the creation of heterostructures based on graphene and other two-dimensional crystals, which can be assembled into three-dimensional stacks with atomic layer precision(5-7). Such layered structures have already demonstrated a range of fascinating physical phenomena(8-71), and have also been used in demonstrating a prototype field-effect tunnelling transistor(12), which is regarded to be a candidate for post-CMOS (complementary metal-oxide semiconductor) technology. The range of possible materials that could be incorporated into such stacks is very large. Indeed, there are many other materials with layers linked by weak van der Waals forces that can be exfoliated(3,13) and combined together to create novel highly tailored heterostructures. Here, we describe a new generation of field-effect vertical tunnelling transistors where two-dimensional tungsten disulphide serves as an atomically thin barrier between two layers of either mechanically exfoliated or chemical vapour deposition-grown graphene. The combination of tunnelling (under the barrier) and thermionic (over the barrier) transport allows for unprecedented current modulation exceeding 1 x 10(6) at room temperature and very high ON current. These devices can also operate on transparent and flexible substrates.

Vertical field-effect transistor based on graphene?WS2 heterostructures for flexible and transparent electronics

Steep subthreshold swing transistors based on interband tunneling are examined toward extending the performance of electronics systems. In particular, this review introduces and summarizes progress in the development of the tunnel field-effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges. The promise of the TFET is in its ability to provide higher drive current than the MOSFET as supply voltages approach 0.1 V.

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Low-Voltage Tunnel Transistors for Beyond CMOS Logic

A formula is derived, which shows that the subthreshold swing of field-effect interband tunnel transistors is not limited to 60 mV/dec as in the MOSFET. This formula is consistent with two recent reports of interband tunnel transistors, which show lower than 60-mV/dec subthreshold swings and provides two simple design principles for configuring these transistors. One of these principles suggests placing the gate adjacent to the tunnel junction. Modeling of this configuration verifies that sub-60-mV/dec swing is possible.

Low-subthreshold-swing tunnel transistors

A graphene nanoribbon (GNR) tunnel field-effect transistor (TFET) is proposed and modeled analytically. Ribbon widths between 3 and 10 nm are considered to effect energy bandgaps in the range of 0.46 to 0.14 eV. It is shown that a 5-nm ribbon width TFET can switch from on to off with only 0.1-V gate swing. The transistor achieves 800 muA/mum on -state current and 26 pA/mum off-state current, with an effective subthreshold swing of 0.19 mV/dec. Compared to a projected 2009 n MOSFET, the GNR TFET can provide 5times higher speed, 20times lower dynamic power, and 280 000times lower off-state power dissipation. The high performance of GNR TFETs results from their narrow bandgaps and their 1-D nature.

/pdf/graphene-nanoribbon-tunnel-transistors-24aha4bo37.pdf

Graphene Nanoribbon Tunnel Transistors

We determined the band alignment of a graphene-insulator-semiconductor structure using internal photoemission spectroscopy. From the flatband voltage and Dirac voltage, we infer a 4.6× 1011cm−2 negative extrinsic charge present on the graphene surface. Also, we extract the graphene work function to be 4.56 eV, in excellent agreement with theoretical and experimental values in literature. Electron and hole injection from heavily doped p-type silicon (Si) are both observed. The barrier height from the top of the valence band of Si to the bottom of the conduction band of silicon dioxide (SiO2) is found to be 4.3 eV. The small optical absorption in graphene makes it a good transparent contact to enable the direct observation of hole injection from Si to graphene. The barrier height for holes escaping from the bottom of Si conduction band to the top of SiO2 valence band is found to be 4.6 eV.

/pdf/determination-of-graphene-work-function-and-graphene-20jd5vy0rr.pdf

Determination of graphene work function and graphene-insulator-semiconductor band alignment by internal photoemission spectroscopy

Vertical tunnel field-effect transistors (TFETs) in which the gate field is aligned with the tunneling direction have been fabricated using a novel gate-recess process, resulting in record on-current. The tunnel junction consists of InAs/GaSb with a broken band alignment. The gate-recess process results in low drain contact and access resistances; together with the favorable broken gap heterojunction, this leads to a record high I ON of 180 μA/μm at V DS = V GS = 0.5 V with an Ion/Ioff ratio of 6 ×103. Both SiN x passivation and forming gas anneal (FGA) were found to improve the device subthreshold swing (SS), resulting in a SS MIN of 200 mV/dec at 300 K and 50 mV/dec at 77 K. Capacitance-voltage (C-V) measurements indicate that the device SS performance is limited by interfacial trap density (D it ).

Qin Zhang

Papers

Low-Voltage Tunnel Transistors for Beyond CMOS Logic

Low-subthreshold-swing tunnel transistors

Graphene Nanoribbon Tunnel Transistors

Determination of graphene work function and graphene-insulator-semiconductor band alignment by internal photoemission spectroscopy

Novel gate-recessed vertical InAs/GaSb TFETs with record high I ON of 180 μA/μm at V DS = 0.5 V