We take a fresh look at the problems posed by deep submicron (DSM) geometries and re-open the investigation into how DSM effects are most likely to affect future design methodologies. We describe a comprehensive approach to accurately characterize the device and interconnect characteristics of present and future process generations. This approach results in the generation of a representative strawman technology that is used in conjunction with analytical model simulation tools and empirical design data to obtain a realistic picture of the future of circuit design. We then proceed to quantify the precise impact of interconnect, including delay degradation due to noise, on high performance ASIC designs. Having determined the role of interconnect in performance, we then reconsider the impact of future processes on ASIC design methodology.

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Getting to the bottom of deep submicron

Process effects in deep-submicrometer geometries are expected to change the physical organization, or microarchitecture, of integrated circuits. The factor that is expected to primarily impact integrated circuit microarchitectures is increasing delays in interconnect. We believe that, to properly microarchitect integrated circuits in small process geometries, it is necessary to get as detailed a picture as possible of the effects and then to draw conclusions about changes in microarchitecture. To this end, in this paper we describe a comprehensive approach to accurately characterizing the device and interconnect characteristics of present and future process generations. This approach uses a detailed extrapolation of future process technologies to obtain a realistic view of the future of circuit design. We then proceed to quantify the precise impact of interconnect, including dynamic delay due to noise, on the performance of high-end integrated circuit designs. Having determined this, we then reconsider the impact of future processes on integrated-circuit design methodology. We determine that local interconnect effects can be managed through a deep-submicrometer design hierarchy that uses 50 K-100 K gate modules as primitive building blocks. In light of this new system-on-a-chip microarchitecture, we then examine global interconnect issues. Our results indicate that, while global communication speeds will necessarily be lower than local clock speeds, international Technology Roadmap for Semiconductors expectations should be attainable to the 0.05-/spl mu/m technology generation. Achieving these high clock speeds (10 GHz local clock) will be aided by the use of a newly proposed routing hierarchy that limits interconnect effects at each level of a design (local, isochronous, and global). In addition, key components of the interconnect architecture of the future include fat (or unscaled) global wires, intelligent repeater and shield wire insertion, and efficient packaging technologies.

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Impact of small process geometries on microarchitectures in systems on a chip

The density and performance of advanced silicon technologies have made system-on-a-chip ASICs possible. SoCs bring together a diverse set of functions and technology features on a single die of enormous complexity. The physical design of these complex ASICs requires a rich set of functional elements that integrate efficiently with a set of design flows and tools productive enough to meet product requirements successfully, without consuming more time or design resources than a simpler design. The architecture described, including functional libraries and physical design conventions, enables the creation of multiple SoC ASIC designs from a common infrastructure that addresses silicon integration, electrical robustness, and packaging challenges. An implementation strategy follows from this design infrastructure that includes hierarchical design concepts, placement, routing, and verification processes.

Issues and strategies for the physical design of system-on-a-chip ASICs

The experience of designing and employing two benchmark circuits to improve the quality of a standard cell library is reported. It is found that most of the errors can be uncovered by making use of these two benchmark circuits to port the underlying cell library to the target environment. Two releases of a 0.25 /spl mu/m standard cell library have been tested by these two benchmark circuits to ensure their quality.

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Benchmark circuits improve the quality of a standard cell library

An integrated computer-aided design (CAD) framework for evaluating MOSFET and layout parasitic extraction (LPE) models and circuit simulators used in the timing and power analysis of CMOS products is presented. This unified CAD methodology builds a step-wise understanding of the underlying parameter values in the models and their impact on circuit performance. A number of circuit experiments are included to extract the contributions of key MOSFET parameters and physical layout sensitive parasitic elements from circuit simulation results. This CAD setup thus allows easy and detailed comparison of different technologies, device models, and LPE tools to prevent possible bugs in the software as well as inaccuracies in device and parasitic models and timing tools. The software code to carry out the circuit simulations, analysis, and display of the results in an automated fashion has been specifically developed to support this framework. Some of the experiments designed for this work are also placed on the product chip for model-to-hardware correlation. The comparison of the hardware data to the model predictions points to the sources of any discrepancies and aids in tuning the product design to reflect changes in the technology as part of an overall design for manufacturing (DFM) platform

An Integrated CAD Methodology for Evaluating MOSFET and Parasitic Extraction Models and Variability

A library strategy has been developed to enable IBM Microelectronics ASIC development to keep pace with rapid technology enhancements and to offer leading-edge performance to ASIC customers. Library elements are designed using migratable design rules to allow designs to be reused in future advanced technologies; and library contents, design methodology, test methodology, and packaging offerings for the ASICs also are consistent between current and future technologies. The benefit to the ASIC customer is an ASIC with a rich library of logic functions, arrays, and I/Os for today's designs, and with a ready migration path into future designs.

R. A. Piro

Papers

Technology-migratable ASIC library design