The incorporation of impurities into solids by bombardment with energetic ions is a non-equilibrium process which can result in intriguing near-surface property changes. This review initially examines the basic ion-solid interaction processes and outlines how such processes can lead to the modification of the composition, structure and surface topography of materials. Ion implantation has been exploited in widely diverse fields both as a powerful research tool for investigating solid state material processes and properties, and as a means of controllably modifying the electrical, physical, chemical, mechanical and optical properties of solid surfaces. These aspects receive major attention in this review which attempts to provide a balanced overview of the impact of ion implantation on solid state science and technology. In particular, special emphasis is given to implantation processes and applications in semiconductors which have received an enormous amount of attention in recent years, stimulated no doubt by the strong technological driving forces within the microelectronics industry. Ion bombardment processes and interesting property changes in metals are also discussed, and a selection of important technological applications is given. Finally, an overview of more recent investigations and applications is presented, including ion implantation into insulators and polymers, insight into crystal growth processes, adhesion of thin films to substrates, and research into ion bombardment of ices which has astrophysical significance.

https://iopscience.iop.org/article/10.1088/0034-4885/49/5/001/pdf

Materials modification with ion beams

Elastic stresses are frequently induced in GaAs substrates during the fabrication of FET's, particulariy in the vicinity of windows in dielectric overlayers. It is shown here that these stresses can produce piezoelectric charge densities of such magnitude to appreciably shift the pinchoff voltage and saturation current of FET's. These shifts are of opposite sign for FET's oriented along [011] and [011] directions on

Piezoelectric effects in GaAs FET's and their role in orientation-dependent device characteristics

Recently developed modulation-doped field-effect transistors (MODFETs) now hold the record for high-speed logic. In this device structure only the larger bandgap (Al,Ga)As layer is doped with donors and the GaAs layer is left undoped. Electrons minimize their energy by diffusing out of the (Al,Ga)As into the lower potential GaAs where they form a two-dimensional electron gas near the heterointerface. Since the electrons and donors are spatially separated, ionized impurity scattering is avoided making it possible to obtain extremely high electron mobilities. Even at electron densities of 1019cm-3or ∼ 1 × 1012cm-2per interface, transport properties of these heterostructures are comparable to pure bulk GaAs. Modulation-doped FETs using this heterojunction system offer many advantages among which are a small gate to conducting channel separation (∼ 300 A) leading to extremely high transconductances, a large current-carrying capability (∼ 500 mA/mm per interface), a small source resistance, and a small saturation voltage. The benefits improve quite substantially at 77 K where the transconductance increases to ∼ 500 mS/mm. Improved device performance has been obtained in both high-speed and digital applications. Modulation-doped FETs used as low-noise amplifiers exhibit noise figures as low as 0.4 dB with 14-dB gain at 10 GHz at 77 K and a noise temperature of 3.5 K at 3.3 GHz with the MODFET cooled to 15 K. The rate of increase in noise temperature is about 1 K/GHz. Quarter micrometer devices have exhibited a current-gain cutoff frequency of 70 GHz. When used as inverters in logic circuits, propagation delays of 12 ps and under 10 ps have been obtained at 300 and 77 K, respectively. Delay times as low as 5 ps are quite possible at 77 K. Static RAMs with 4-kbit complexity exhibited access times of about 2 ns. These results are far superior to any other three-terminal device which is the primary reason why numerous university, industrial, and government laboratories in the U.S., Europe, and Japan have sizable MODFET programs.

Modulation-doped GaAs/(Al,Ga)As heterojunction field-effect transistors: MODFETs

The traveling wave potential wells, associated with a surface acoustic wave (SAW) generated in a multilayer epitaxial GaAs structure, are used to transport electrons at the velocity of sound in the buried channel formed by a Schottky‐N‐P layer configuration. A monolithic delay line based on the SAW transport concept is constructed and the time domain response of the delay line is presented. The SAW charge transport concept in GaAs is expected to be useful for the implementation of high‐speed monolithic signal processors.

Charge transport by surface acoustic waves in GaAs

We have demonstrated a new type of buried‐channel acoustic charge transport device in which charge is transported in an (Al,Ga)As/GaAs/(Al,Ga)As heterojunction channel. Traveling‐wave potential wells, associated with a surface acoustic wave (SAW) propagating on the 〈100〉 surface of a GaAs crystal, transport electrons at the SAW velocity by means of a large‐signal acoustoelectric interaction. Heterojunction acoustic charge transport (HACT) delay lines have been fabricated, and the transport of charge demonstrated. Charge packets with up to 16×106 electrons/cm were measured in a delay 1.4 μs long. The HACT device is much simpler, the transport channel is more reliably produced (by molecular beam epitaxy or metalorganic chemical vapor deposition), and the device has potential for higher dynamic range when compared to the previously developed acoustic charge transport technology. This new device type is useful for the implementation of high‐speed monolithic signal processors.

Heterojunction acoustic charge transport devices on GaAs

A planar GaAs integrated circuit (IC) fabrication technology capable of LSI complexity has been developed. The circuit and fabrication approaches were chosen to satisfy LSI requirements for high yield, high density, and low power. This technology utilizes Schottky-diode FET logic (SDFL) incorporating both high-speed switching diodes and 1-µ m GaAs MESFET's. Circuits are fabricated directly on semi-insulating GaAs using multiple localized implantations. Rapid progress in the development of this technology has already led to the successful demonstration of high-speed ( \tau_{d} \sim 100 ps) low-power (∼500 µW/gate) GaAs MSI (∼60-100 gates) circuits. Extension of the current MSI technology to the LSI/VLSI domain will depend critically on device yield which will be dictated by the GaAs material properties and by the fabrication processes used. The purpose of this paper is to describe a GaAs IC process technology which combines advanced planar device and multilevel interconnect structures with several LSI compatible processes including multiple localized ion implantations, reduction photolithography, plasma etching, reactive ion etching, and ion milling.

LSI processing technology for planar GaAs integrated circuits

A Schottky-barrier gate GaAs charge-coupled device (CCD) technology is described. Experimental devices fabricated in this technology have operated with charge transfer efficiency >0.999/transfer and-have operated at clock frequency f_{cl} = 500 MHz. Implications of this technology in high-speed signal processing and in visible and near-infrared imaging are discussed.

GaAs and related heterojunction charge-coupled devices

The successful development of a new integrated circuit (IC) technology requires a significant effort in process evaluation. This is particularly true for the high-speed low-power planar GaAs digital IC technology, which involves a relatively new semiconductor material, new processing techniques, and pursues LSI complexity using very-fine-line lithography (1-µm dimensions). This paper contains a review of the strategy employed to monitor and evaluate each of the key process steps, and to evaluate the uniformity of device parameters. The principal process evaluation test structures are discussed along with measurement techniques, and examples of measurement results are given. Our emphasis on measurement automation to facilitate the collection of a large volume of data and their statistical analysis is reflected in the paper. Examples of wafer statistics are given.

Process evaluation test structures and measurement techniques for a planar GaAs digital IC technology

A new approach to the design and fabrication of GaAs digital integrated circuits capable of high speed and low power dissipation has been demonstrated This technology relies on Schottky-diode FET logic (SDFL) circuits which take advantage of the high switching speed of Schottky diodes and the high transconductance of the GaAs 1-µm gate MESFET These circuits are fabricated by localized implantations directly into the semi-insulating GaAs substrate Excellent results in terms of speed and power dissipation have been achieved, while circuit complexity has lrapidly grown as demonstrated by the successful operation of an eight-channel multiplexer, an eight-channel demultiplexer, and a 3 × 3 parallel multiplier employing 64, 60, and 75 gates, respectively This rapid progress requires considerable work in monitoring the process through statistical evaluation of test devices This paper discusses the process monitoring work carried out in support of the technology, The organization of the masks used for circuit development is described, with emphasis on process monitoring test patterns Automatic instrumentation used to gather a large amount of statistical information is described, and wafer maps illustrating statistical results are presented and discussed Uniformity of device characteristics over the full wafer and over smaller areas (circuit size) is compared Implications of these results are discussed in terms of circuit yield

MP-A3 GaAs digital IC technology/Statistical analysis of device performance

The extraordinary progress which has taken place in GaAs digital IC technology over the last two years is reviewed, highlighting the role of the semi-insulating substrate. The most critical requirements of the material are discussed in the context of current circuit fabrication techniques. At the same time, recent advances in the fundamental knowledge of the material are briefly reviewed and weighted according to their impact on the technology.

R.C. Eden

Papers

LSI processing technology for planar GaAs integrated circuits

GaAs and related heterojunction charge-coupled devices

Process evaluation test structures and measurement techniques for a planar GaAs digital IC technology

MP-A3 GaAs digital IC technology/Statistical analysis of device performance

Semi-Insulating GaAs — a User’s View