The incorporation of impurities into solids by bombardment with energetic ions is a non-equilibrium process which can result in intriguing near-surface property changes. This review initially examines the basic ion-solid interaction processes and outlines how such processes can lead to the modification of the composition, structure and surface topography of materials. Ion implantation has been exploited in widely diverse fields both as a powerful research tool for investigating solid state material processes and properties, and as a means of controllably modifying the electrical, physical, chemical, mechanical and optical properties of solid surfaces. These aspects receive major attention in this review which attempts to provide a balanced overview of the impact of ion implantation on solid state science and technology. In particular, special emphasis is given to implantation processes and applications in semiconductors which have received an enormous amount of attention in recent years, stimulated no doubt by the strong technological driving forces within the microelectronics industry. Ion bombardment processes and interesting property changes in metals are also discussed, and a selection of important technological applications is given. Finally, an overview of more recent investigations and applications is presented, including ion implantation into insulators and polymers, insight into crystal growth processes, adhesion of thin films to substrates, and research into ion bombardment of ices which has astrophysical significance.

https://iopscience.iop.org/article/10.1088/0034-4885/49/5/001/pdf

Materials modification with ion beams

Elastic stresses are frequently induced in GaAs substrates during the fabrication of FET's, particulariy in the vicinity of windows in dielectric overlayers. It is shown here that these stresses can produce piezoelectric charge densities of such magnitude to appreciably shift the pinchoff voltage and saturation current of FET's. These shifts are of opposite sign for FET's oriented along [011] and [011] directions on

Piezoelectric effects in GaAs FET's and their role in orientation-dependent device characteristics

Temperature profile and thermal stress calculations in GaAs crystals growing from the melt

Conditions for post‐implantation capless annealing of GaAs, called infrared rapid thermal annealing (IRTA) using halogen lamps, were investigated. Si‐implanted GaAs (5×1012 cm−2, 150 keV) was annealed at temperatures ranging from 700 to 1100 °C for various annealing times. Annealed GaAs at 950 °C for 2–4 s shows about 75% electrical activation and 3700 cm2/Vs electron mobility without noticeable dopant diffusion and surface decomposition. Planar metal‐semiconductor field‐effect transistors (MESFET’s) fabricated on the active layer formed by this annealing method show that the technique is promising as a post‐implantation annealing method for the fabrication of GaAs MESFET’s and GaAs integrated circuits (IC’s).

Infrared rapid thermal annealing of Si‐implanted GaAs

Much interest has been expressed in the use of GaAs MESFET's for high speed digital integrated circuits (IC's). Propagation delays in the 60- to 90-ps/gate range have been demonstrated by several laboratories on SSI and MSI logic circuits. Recently, large scale digital IC's with over 1000 gates have been demonstrated in GaAs. In this review paper, the device, circuit, and processing approaches presently being explored for high speed GaAs digital circuits are presented. The present performance status of high speed circuits and LSI circuits is reviewed.

High speed GaAs integrated circuits

A planar GaAs integrated circuit (IC) fabrication technology capable of LSI complexity has been developed. The circuit and fabrication approaches were chosen to satisfy LSI requirements for high yield, high density, and low power. This technology utilizes Schottky-diode FET logic (SDFL) incorporating both high-speed switching diodes and 1-µ m GaAs MESFET's. Circuits are fabricated directly on semi-insulating GaAs using multiple localized implantations. Rapid progress in the development of this technology has already led to the successful demonstration of high-speed ( \tau_{d} \sim 100 ps) low-power (∼500 µW/gate) GaAs MSI (∼60-100 gates) circuits. Extension of the current MSI technology to the LSI/VLSI domain will depend critically on device yield which will be dictated by the GaAs material properties and by the fabrication processes used. The purpose of this paper is to describe a GaAs IC process technology which combines advanced planar device and multilevel interconnect structures with several LSI compatible processes including multiple localized ion implantations, reduction photolithography, plasma etching, reactive ion etching, and ion milling.

LSI processing technology for planar GaAs integrated circuits

A new approach to the design and fabrication of GaAs digital integrated circuits capable of high speed and low power dissipation has been demonstrated This technology relies on Schottky-diode FET logic (SDFL) circuits which take advantage of the high switching speed of Schottky diodes and the high transconductance of the GaAs 1-µm gate MESFET These circuits are fabricated by localized implantations directly into the semi-insulating GaAs substrate Excellent results in terms of speed and power dissipation have been achieved, while circuit complexity has lrapidly grown as demonstrated by the successful operation of an eight-channel multiplexer, an eight-channel demultiplexer, and a 3 × 3 parallel multiplier employing 64, 60, and 75 gates, respectively This rapid progress requires considerable work in monitoring the process through statistical evaluation of test devices This paper discusses the process monitoring work carried out in support of the technology, The organization of the masks used for circuit development is described, with emphasis on process monitoring test patterns Automatic instrumentation used to gather a large amount of statistical information is described, and wafer maps illustrating statistical results are presented and discussed Uniformity of device characteristics over the full wafer and over smaller areas (circuit size) is compared Implications of these results are discussed in terms of circuit yield

MP-A3 GaAs digital IC technology/Statistical analysis of device performance

High-speed divider circuits find numerous applications in prescalers for counters, frequency synthesizers, and digital phase locked loops. To accommodate these applications, a high-speed multimode divider circuit has been designed, fabricated, and tested. This circuit, fabricated on semi-insulating Gallium Arsenide substrates, and utilizing Schottky diode FET logic (SDFL) technology, has been tested at a maximum clock frequency of 1.84 GHz. High yields of circuits operating over 1 GHz have been obtained over a number of wafers.

High-speed GaAs SDFL divider circuit

The extraordinary progress which has taken place in GaAs digital IC technology over the last two years is reviewed, highlighting the role of the semi-insulating substrate. The most critical requirements of the material are discussed in the context of current circuit fabrication techniques. At the same time, recent advances in the fundamental knowledge of the material are briefly reviewed and weighted according to their impact on the technology.

R. Zucca

Papers

LSI processing technology for planar GaAs integrated circuits

MP-A3 GaAs digital IC technology/Statistical analysis of device performance

High-speed GaAs SDFL divider circuit

Semi-Insulating GaAs — a User’s View

High-Speed GaAs SDFL Divider Circuit