Journal ArticleDOI
Drift of the breakdown voltage in p-n junctions in silicon (walk-out)
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TLDR
In this paper, a quantitative model for the time behaviour of the walk-out phenomenon in planar p - n junctions is given, where the injection of hot carriers into SiO 2 and subsequent trapping of part of them is assumed to be the origin of walkout.Abstract:
A quantitative model for the time behaviour of the walk-out phenomenon in planar p - n junctions is given. The injection of hot carriers into SiO 2 and subsequent trapping of part of them is assumed to be the origin of the walk-out. The model is found to be in reasonable agreement with the experimental results on both p + − n and n + − p junctions. The parameters in the model are discussed in relation with the experiments.read more
Citations
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Journal ArticleDOI
Impact ionization in silicon: A review and update
TL;DR: In this paper, the authors define the multiplication factor and the ionization rate together with their interrelationship, multiplication and breakdown models for diodes and MOS transistors.
Journal ArticleDOI
Trench DMOS transistor technology for high-current (100 A range) switching
TL;DR: In this article, the authors present the development of rugged high-current (100 A range) low-voltage trench DMOS transistors, featuring 4 mΩ on-resistance, with controlled bulk avalanche breakdown at 70 V and gate dielectric breakdown at 60 V.
Journal ArticleDOI
Optimization and surface charge sensitivity of high-voltage blocking structures with shallow junctions
TL;DR: The most commonly used high-voltage blocking and termination structures-floating field limiting rings (FLR), lateral charge control HVIC devices, and junction termination extension (JTE) structures-are very sensitive to positive silicon and silicon dioxide interface charges as mentioned in this paper.
Journal ArticleDOI
Junction degradation in bipolar transistors and the reliability imposed constraints to scaling and design
Denny D. Tang,E. Hackbarth +1 more
TL;DR: In this article, the reverse-stress-induced junction degradation can be eliminated by properly designing the circuit when the logic swing is less than the V/sub be/ of the transistors.
Journal ArticleDOI
Drain-avalanche and hole-trapping induced gate leakage in thin-oxide MOS devices
TL;DR: In this paper, leakage current components due to band-to-band tunneling and avalanche breakdown in thin-oxide (90-160 AA) gated-diode structures are discussed.
References
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Journal ArticleDOI
Capture cross section and trap concentration of holes in silicon dioxide
TL;DR: In this paper, hole trapping in thermally grown silicon dioxide films has been studied using optically induced hot-hole injection in p-channel polysilicon-SiO2-silicon field effect transistor structures.
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Electron trapping at positively charged centers in SiO2
T. H. Ning,C. M. Osburn,H. N. Yu +2 more
TL;DR: In this article, it was shown that positive oxide charge centers in thin films of thermally grown silicon dioxide are electron traps with an average capture cross section of 3±2×10−13 cm2 at room temperature and at an average oxide field of about 7×105 V/cm.
Journal ArticleDOI
Hole Currents in Thermally Grown SiO2
TL;DR: In this paper, the current of holes injected into thermally grown SiO2 from a planar avalanching p−n junction was investigated and it was shown that the current seems to be limited by a bulk process, viz., field-assisted thermal emission from traps in the SiO 2 (Poole-Frenkel conduction).
Journal ArticleDOI
The origin of channel currents associated with P + regions in silicon
A.S. Grove,D.J. Fitzgerald +1 more
TL;DR: In this article, the breakdown of the field-induced junction formed between the inversion layer and the underlying P+region was studied experimentally in detail, and it was shown that breakdown can proceed through either a tunneling or an avalanche mechanism depending on the surface concentration of the p+region.
Journal ArticleDOI
Avalanche injection into the oxide in silicon gate-controlled devices—I theory
TL;DR: In this paper, the authors analyzed the hot-carrier injection ratio (avalanche-induced gate current over junction current) at given maximum interface electric field at breakdown, in terms of the physical theory of hot electrons in silicon.