VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

· Most up-to-date coverage of design for testability. 
· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. 
· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
· Lecture slides and exercise solutions for all chapters are now available.
· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

Table of Contents

Chapter 1 - Introduction
Chapter 2 - Design for Testability
Chapter 3 - Logic and Fault Simulation 
Chapter 4 - Test Generation 
Chapter 5 - Logic Built-In Self-Test
Chapter 6 - Test Compression
Chapter 7 - Logic Diagnosis
Chapter 8 - Memory Testing and Built-In Self-Test
Chapter 9 - Memory Diagnosis and Built-In Self-Repair
Chapter 10 - Boundary Scan and Core-Based Testing
Chapter 11 - Analog and Mixed-Signal Testing
Chapter 12 - Test Technology Trends in the Nanometer Age

VLSI Test Principles and Architectures: Design for Testability

A unified notation is presented for static random access memory (SRAM) fault models and fault tests for these models. The likelihood that the different types of faults will occur is demonstrated using inductive fault analysis and physical defect analysis. A set of march tests is discussed, together with methods to make composite tests for collections of fault tapes. Empirical results showing the fault coverage of the different test enable SRAM users to choose the fault models of interest as well as the test. >

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Using march tests to test SRAMs

Testing static random access memories (SRAMs) for all possible failures is not feasible and one must restrict the class of faults to be considered. This restricted class is called a fault model. A fault model for SRAMs based on physical spot defects, which are modeled as local disturbances in the layout of the SRAM, is presented. Two linear test algorithms that cover 100% of the faults under the fault model are proposed. A general solution is given for testing word-oriented SRAMs. The practical validity of the fault model and the two test algorithms are verified by a large number of actual wafer tests and device failure analyses. >

A realistic fault model and test algorithms for static random access memories

For pt.1 see ibid., vol.10, no.1, p.73-82 (1993). The hardware structures and tools used to implement built-in self-test (BIST) pattern generation and response analysis concepts are reviewed. The authors describe testing approaches for general and structured logic, including ROMs, RAMs, and PLAs. They illustrate BIST techniques with real-world examples. >

A tutorial on built-in self-test. 2. Applications

A fault model for SRAMs (static random-access memories) is presented based on physical spot defects, which are modeled as local disturbances in the layout of an SRAM. Two linear test algorithms (length 9N and 13N respectively, where N is the number of addresses) plus a data retention test are proposed that cover 100% of the faults under the fault model. The 13N test algorithm is generally applicable while the 9N algorithm can only be used in SRAMs with combinational R/W logic. A general solution is given for testing word-oriented SRAMs. The practical validity of the fault model and the two test algorithms is verified by a large number of actual wafer tests and device failure analysis. >

Fault modeling and test algorithm development for static random access memories

A self-test machine for static random access memories (SRAMs) has been developed. It is capable of running linear test algorithms, generating a at a retention test and generating a number of data backgrounds. The test algorithm implemented has excellent fault-detection capabilities and is extremely regular and symmetric, which results in a minimum of hardware overhead and performance loss. Self-test reduces the possibilities for diagnostic tests. A form of scan test remains necessary in spite of a self-test implementation. This self-test design offers full scan test facilities of both the SRAM and the self-test logic itself. This version of the SRAM self-test is currently being implemented in a number of digital signal processing chips and will, after a final evaluation, be used for a broad scope of designs. >

A realistic self-test machine for static random access memories

The authors present the specification and design of a self-test mechanism for static random-access memories (RAMs). The test algorithm provides excellent fault detection, and its structure is independent of address and data scrambling. The self-test machine generates data backgrounds on chip and is therefore suitable for both bit-oriented and word-oriented SRAMs. It is also suitable for both embedded SRAMs and stand-alone SRAMs, and adapts to boundary-scan environment. Because of the regular and symmetric structure of the test algorithm, the silicon overhead is only 3% for a 16 K synchronous SRAM. >

R. Dekker

Papers

A realistic fault model and test algorithms for static random access memories

Fault modeling and test algorithm development for static random access memories

A realistic self-test machine for static random access memories

Realistic built-in self-test for static RAMs

Fault Modeling and Test Algorithm Development.