We live in a world where technological advances are continually creating more data than what we can deal with. Machine learning algorithms, in particular Deep Neural Networks (DNNs), are essential to process such large data. Computation of DNNs requires loading the trained network on the processing element and storing the result in memory. Therefore, running these applications need a high memory bandwidth. Traditional cores are memory limited in terms of the memory bandwidth. Hence, running DNNs on traditional cores results in high energy consumption and slows down processing speed due to a large amount of data movement between memory and processing units. Several prior works tried to address data movement issue by enabling Processing In-Memory (PIM)using crossbar analog multiplication. However, these designs suffer from the large overhead of data conversion between analog and digital domains. In this work, we propose RNSnet, which uses Residue Number System (RNS)to execute neural network completely in the digital domain in memory. RNSnet simplifies the fundamental neural network operations and maps them to in-memory addition and data access. We test the efficiency of the proposed design on several popular neural network applications. Our experimental result shows that RNSnet consumes 145.5x less energy and obtains 35.4x speedup as compared to NVIDIA GPU GTX 1080. In addition, our results show that RNSnet can achieve 8.5 x higher energy-delay product as compared to the state-of-the-art neural network accelerators.

https://par.nsf.gov/servlets/purl/10100787

RNSnet: In-Memory Neural Network Acceleration Using Residue Number System

Full Adder (FA) circuits are integral components in the design of Arithmetic Logic Units (ALUs) of modern computing systems. Recently, there have been massive research interests in this area due to the growing need for low-power and high-performance computing systems. Researchers have proposed a variety of FA cells with diverse design techniques, each having its pros and cons. As a result, a systematic method for performance comparison of FA cells using a common simulation platform has become necessary. In this work, we present an extensive study of FA cells. We have compared the performance of thirty-three (33) existing 1-bit FA cells. The drive powers of these FA cells have been compared by applying a variety of load conditions. In addition, the 1-bit FA cells have been extended to 32-bit structures to test their scalability and to investigate their performance in wide-word structures. We have determined that twenty-one (21) of the thirty-three (33) FA cells cannot operate in a 32-bit structure, even though some of them exhibit excellent performance as a 1-bit cell. The main finding of this research is that the single-bit performance parameters of FA cells should not be considered as the main basis for performance comparison. Any FA cell should be analyzed in a multi-bit structure to determine its practical effectiveness.

/pdf/comprehensive-study-of-1-bit-full-adder-cells-review-2p2d8wn4jc.pdf

Comprehensive study of 1-Bit full adder cells: review, performance comparison and scalability analysis

Remote computing has emerged as a trendy computing model that enables users to process an immense number of computations efficiently on the remote server where the necessary data and high-performance computing power are provisioned. Unfortunately, despite such an advantage, this computing model suffers from insider threats that are committed by adversarial administrators of remote servers who attempt to steal or corrupt users’ private data. These security threats are somewhat innate to remote computing in that there is no means to control administrators’ unlimited data access. In this paper, we present our novel hardware-centric solution, called MeetGo , to address the intrinsic threats to remote computing. MeetGo is a field-programmable gate array (FPGA)-based trusted execution environment (TEE) that aims to operate independently of the host system architecture. To exhibit the ability and effectiveness of MeetGo as a TEE ensuring secure remote computing, we have built two concrete applications: cryptocurrency wallet and GPGPU. MeetGo provides a trust anchor for these applications that enable their users to trade cryptocurrency or to run a GPGPU program server on a remote server while staying safe from threats by insiders. Our experimental results clearly demonstrate that MeetGo incurs only a negligible performance overhead to the applications.

/pdf/meetgo-a-trusted-execution-environment-for-remote-vxe2o3auyw.pdf

MeetGo: A Trusted Execution Environment for Remote Applications on FPGA

Sports image detection based on FPGA hardware system and particle swarm algorithm

In this paper it is introduced an automatic Thai coin calculation system based on image processing technique. It shown that our sytem can classify and calculate the total value of coins that is useful for the blind persons. Image processing used for detection coins in first. After that, SIFT key-points algorithm is used to classification and matching with sound. This system used four types of popular Thai coin in the experimental. We designed our experimental in the different case. In each case, there are different type coin. The least amount of coins is 5 to 40. The accuracy rate shown 99%.

Automatic Thai Coin Calculation System by Using SIFT

Serial Peripheral Interface is a synchronous protocol that allows serial communication between a master and a slave device. The purpose of this paper is to provide a full description of a high speed SPI Master/Slave implementation. The designs are based on Motorola's SPI Block Guide V03.06. This paper discusses design approaches that can offer prospective ways of controlling SPI-bus, incorporating the flexibility of handling two slaves at a time. Starting from the initial specifications till the final physical design, the design phases are systematically elaborated. The whole design is implemented in Verilog 2001, and mapped onto Xilinx's Virtex 5 FPGA devices.

Design and implementation of a high speed Serial Peripheral Interface

To represent very large or small values, large range is required as the integer representation is no longer appropriate. These values can be represented using the IEEE-754 standard based floating point representation. This paper presents high speed ASIC implementation of a floating point arithmetic unit which can perform addition, subtraction, multiplication, division functions on 32-bit operands that use the IEEE 754-2008 standard. Prenormalization unit and post normalization units are also discussed along with exceptional handling. All the functions are built by feasible efficient algorithms with several changes incorporated that can improve overall latency, and if pipelined then higher throughput. The algorithms are modeled in Verilog BDL and the RTL code for adder, subtractor, multiplier, divider, square root are synthesized using Cadence RTL complier where the design is targeted for 180nm TSMC technology with proper constraints.

/pdf/vlsi-implementation-of-a-high-speed-single-precision-1ry9yf69sp.pdf

VLSI implementation of a high speed single precision floating point unit using verilog

Implementation of a High Speed Single Precision Floating Point Unit using Verilog

Arithmetic and Logic Unit (ALU) is one of the common and the most crucial components of an embedded system. Power consumption is a major design issue in the case of embedded systems. Usually ALU’s consists of a number of functional units for different arithmetic and logic operations which are realised using combinational circuits. Each of the functional unit performs a specific arithmetic or logic operation. In this paper the main concern is given for reducing the power of the adder and multiplier modules which are important functional units of ALU thereby reducing the overall power consumption without compromising the speed of the processor. The ALU circuit ensures the execution of either arithmetic or logic operation only at a time so that only one set of circuits is active at a time thus ensuring low power consumption. The entire ALU circuit is realised using Verilog HDL and power analysis is obtained through same.

/pdf/design-of-16-bit-low-power-alu-dbgpu-2qua1hskvr.pdf

Design of 16-bit low power alu - dbgpu

This paper proposes implementation of IEEE floating point (FP) multiplication, addition and subtraction Arithmetic on IEEE FP numbers imposes more challenges compared to fixed-point arithmetic These particularly include the simultaneous computation of normalization and rounding We show the efficient way of solving these challenges for the implementation of floating point (FP) addition, subtraction and multiplication The proposed designs aim at reducing power dissipation Here multi threshold voltage technique is used for reducing power dissipation The proposed implementations are according to the IEEE 754 FP standard

R. Dhanabal

Papers

Design and implementation of a high speed Serial Peripheral Interface

VLSI implementation of a high speed single precision floating point unit using verilog

Implementation of a High Speed Single Precision Floating Point Unit using Verilog

Design of 16-bit low power alu - dbgpu

Design and implementation of low power floating point arithmetic unit