The problem of achieving compact, high-performance forced liquid cooling of planar integrated circuits has been investigated. The convective heat-transfer coefficient h between the substrate and the coolant was found to be the primary impediment to achieving low thermal resistance. For laminar flow in confined channels, h scales inversely with channel width, making microscopic channels desirable. The coolant viscosity determines the minimum practical channel width. The use of high-aspect ratio channels to increase surface area will, to an extent, further reduce thermal resistance. Based on these considerations, a new, very compact, water-cooled integral heat sink for silicon integrated circuits has been designed and tested. At a power density of 790 W/cm2, a maximum substrate temperature rise of 71°C above the input water temperature was measured, in good agreement with theory. By allowing such high power densities, the heat sink may greatly enhance the feasibility of ultrahigh-speed VLSI circuits.

High-performance heat sinking for VLSI

In this paper we present a generalized scaling theory which allows for an independent scaling of the FET physical dimensions and applied voltages, while still maintaining constant the shape of the electric-field pattern. Thus two-dimensional effects are kept under control even though the intensity of the field is allowed to increase. The resulting design flexibility allows the design of FET's with quarter-micrometer channel length to be made, for either room temperature or liquid-nitrogen temperature. The physical limitations of the scaling theory are then investigated in detail, leading to the conclusion that the limiting FET performances are not reached at the 0.25-µm channel length. Further improvements are possible in the future, provided certain technology breakthroughs are achieved.

Generalized scaling theory and its application to a &#188; micrometer MOSFET design

The bipolar transistor and FET are compared, considering both today's most advanced implementations and "ultimate" scaled-down devices. The differences between the devices are quantified in terms of transconductance and intrinsic speed. Old limits are re-examined and ways of extending the devices toward their ultimate in performance are proposed. While the major emphasis is on silicon, a comparison is made with the GaAs MESFET. Other semiconductor devices are discussed in the context of "bipolar-like" and "FET-like" devices, and the HEMT is considered a very promising candidate for high-speed logic. While Josephson junction logic is not discussed at length, it is a continual point of reference. In addition to comparing devices, the on-chip wiring environment is discussed, especially concerning its impact on power-delay products.

A comparison of semiconductor devices for high-speed logic

High electric fields, that are characteristic of sub‐micron devices, produce highly energetic electrons, lack of equilibrium between electrons, optical phonons, and acoustic phonons, and high rates of heat generation. A simple coupled thermal and electrical model is developed for sub‐micron silicon semiconductor devices consisting of the hydrodynamic equations for electron transport and energy conservation equations for different phonon modes. An electron Reynolds number is proposed and used to simplify the electron momentum equation. On a case study of the metal‐oxide‐semiconductor field‐effect transistor with 0.24 μm gate length, the calculated transconductance of 0.175 1/Ω m agreed well with measured value of 0.180 1/Ω m at 2 V drain voltage. The maximum electron temperature is found to occur under the drain side of the gate where the electric field is the highest. Comparison with experimental data shows the predictions of optical and acoustic phonon temperature distributions to have the correct trend and the observed asymmetric behavior. Increase in substrate boundary temperature by 100 °C reduces the drain current by 17% and decreases the maximum electron temperature by 8%. The first effect increases device delay and the second effect decreases the possibility of device degradation by charge trapping in the gate oxide.

Concurrent thermal and electrical modeling of sub‐micrometer silicon devices

Publisher Summary This chapter provides an overview of the new techniques for fabrication at a size scale below 100 nm. A number of nanometer-scale devices and scientific studies have become possible with these techniques, and research in this field has seen a number of recent successes. The chapter focuses on the limits and applications of the nanometer-scale fabrication techniques, not their practicality for current device production. The chapter presents the three-dimensional techniques that seem to permit fabrication of structures smaller than 10 nm. However, there are a variety of effects that limit their resolution. The most obvious is penumbra because of limited collimation of the ion beam or evaporant flux. This effect can be eliminated at the cost of reduced flux by simply using apertures or moving the source further from the sample. The chapter also describes the utilization of the third dimension and new three-dimensional lithographic approaches. Such approaches are of clear advantage for achieving high-aspect-ratio patterns, high resolution, and good line width control over a large field of view. When three-dimensional approaches are combined with other self-aligning or self-limiting processes, very powerful device micro-fabrication approaches can be developed.

Chapter 4 - Nanometer-Scale Fabrication Techniques

Electron-beam lithography with a novel multilevel resist structure together with two-dimensional process and device modeling and dry processing with reactive sputter etching have been employed to produce silicon-gate NMOS devices with micrometer and submicrometer channel lengths. Results for transistors and ring oscillators are reported.

Electron-beam lithography for small MOSFET's

We report on measurements and computer simulations for enhancement and depletion MOSFETs with submicron channel lengths as small as 0.2 µm. The behavior of the devices is analyzed using both advanced techniques such as transmission electron microscopy for profile measurements and numerical models to simulate processing conditions and device behavior in two dimensions.

Experimental and theoretical characterization of submicron MOSFETs

We have fabricated MOSFET's with channel lengths as short as 0.1 µm by a modified NMOS process. The devices have been designed according to parameters obtained from numerical simulation. Electron-beam lithography has been used to define patterns at all levels with the negative resist GMC in a tri-level configuration. Heat treatments have been as short as possible to preserve very shallow source-drain junction depths ( L = 0.14 µm, we obtain g_{m} = 180 mS/mm for a gate oxide thickness of 160A.

0.15 &#181;m Channel-length MOSFET's fabricated using e-beam lithography

We present new experimental results on optimally scaled MOSFETs with channel lengths below 0.25 µm. These devices have been fabricated using a modified NMOS process. All patterns have been defined by direct-beam writing using both positive and negative electron resists. The gate oxide thickness of 80A together with properly adjusted ion implantation steps yields device thresholds of 0.5 V. All heat treatments have been kept as short as possible to ensure very shallow source-drain junctions. All contact structures are scaled to 1 × 1 µm window features. Finished devices show excellent performance. Long-channel-like behavior is preserved for supply voltages below 2.5 V. The subthreshold slope is 88 mV/decade. Current drive capabilities are the highest ever reported for silicon MOSFETs. The devices exhibit outstanding transconductance values between 270 and 300 mS/mm.

Optimized MOSFETs with subquartermicron channel lengths

We have fabricated very high speed, low power devices and circuits using a submicron NMOS technology. Our results illustrate the electrical behavior of single minimum size devices, and present the performance of several submicron circuits, such as ring oscillators, a 3 GHz divide-by-two counter and a 90 MHz 16 × 16 multiplier.

R.L. Johnston

Papers

Electron-beam lithography for small MOSFET's

Experimental and theoretical characterization of submicron MOSFETs

0.15 µm Channel-length MOSFET's fabricated using e-beam lithography

Optimized MOSFETs with subquartermicron channel lengths

A submicron NMOS technology suitable for low power high speed circuits

R.L. Johnston

Papers

Electron-beam lithography for small MOSFET's

Experimental and theoretical characterization of submicron MOSFETs

0.15 &#181;m Channel-length MOSFET's fabricated using e-beam lithography

Optimized MOSFETs with subquartermicron channel lengths

A submicron NMOS technology suitable for low power high speed circuits

0.15 µm Channel-length MOSFET's fabricated using e-beam lithography