Showing papers in "IEEE Transactions on Electron Devices in 1981"

Modeling and optimization of monolithic polycrystalline silicon resistors

Abstract: The processing parameters of monolithic polycrystalline silicon resistors are examined, and the effect of grain size on the sensitivity of polysilicon resistivity versus doping concentration is studied theoretically and experimentally. Because existing models for polysilicon do not accurately predict resistivity dependence on doping concentration as grain size increases above 600 A, a modified trapping model for polysilicon with different grain sizes and under various applied biases is introduced. Good agreement between theory and experiments demonstrates that an increase in grain size from 230 to 1220 A drastically reduces the sensitivity of polysilicon resistivity to doping levels by two orders of magnitude. Such an increase is achieved by modifications of the integrated-circuit processes. Design criteria for the optimization of monolithic polysilicon resistors have also been established based on resistivity control, thermal properties, and device geometry.

Hot-electron injection into the oxide in n-channel MOS devices

Abstract: In recent years, interest in hot-electron injection current in MOS devices has increased due to advances in device concepts and technology. The injection current to the gate is the mechanism for programming FAMOS devices and determines the potential degradation of short-channel MOS devices due to electron trapping in the oxide. This work presents an accurate indirect current measurement technique based on charge transport to the floating gate in a FAMOS structure. The measurement bypasses effects of trapping and local heating, allowing full characterization of parameter, voltage, and temperature dependence down to gate current levels of 10-16A. Based on this characterization, a new qualitative model of hot-electron injection into the oxide is proposed. The basic assumption in the model is the spherical symmetry of the momentum distribution function of the hot electrons. This assumption leads to the experimentally observed dominant role of the lateral electric field in the pinchoff region in determining gate current behavior. The model provides an explanation of gate current parameter and voltage dependence, and suggests correlation between gate current and substrate impact ionization current in a range of operating voltages. This correlation is substantiated experimentally for a range of device parameters and voltages.

Threshold-voltage instability in MOSFET's due to channel hot-hole emission

Abstract: Hydrogen introduced and trapped in the gate oxide of MOSFET's by the silicon-nitride capping process can be activated by emitted holes from the MOSFET channel to produce a large threshold-voltage shift. This effect requires avalanche multiplication in the channel for the production of holes when a dc voltage is applied to the gate. For the pulsed-gate case, the magnitude of the threshold-voltage shift depends significantly on the gate-pulse fall time, cycle time, and duty cycle. In both cases the electric field normal to the Si/SiO 2 interface near the drain aids the emission of holes across that interface. A semiquantitative model is proposed which says that holes can recombine at H 2 molecules and release sufficient energy to cause dissociation. The atomic hydrogen created can participate in electrochemical reactions at the gate oxide/channel interface which create nonuniform distributions of trapped charge and interface states along the channel. Model calculations of the time, temperature, and voltage dependences of this threshold instability agree well with measured results.

A study of Pd/Si MIS Schottky barrier diode hydrogen detector

Abstract: Pd/Si MIS Schottky diode hydrogen detectors have been fabricated with a response of 2-3 orders of magnitude change in current for 154 ppm of H 2 in N 2 . Detailed evaluation of dark I-V, C-V, illuminated I-V, and internal photoemission data unambiguously ascribes the strong hydrogen sensitivity of these diodes to hydrogen-induced change in the work function of Pd, rather than to any surface-state effects. The reaction rate of the device to different gas ambients has been studied with time response measurements. A long-term degradation mechanism has been identified and traced to the poisoning of Pd by environmental sulfur. The role of oxygen and atomic hydrogen in determining the Schottky barrier height also is discussed in some detail.

A model for conduction in polycrystalline silicon—Part I: Theory

Abstract: A new phenomenological model for the electrical conduction in polycrystalline silicon is developed. The combined mechanisms of dopant segregation, carrier trapping, and carrier reflection at grain boundaries are proposed to explain the electrical conduction in polycrystalline silicon. The grain boundaries are assumed to behave as an intrinsic wide-band-gap semiconductor forming a heterojunction with the grains. Thermionic emission over the potential barriers created within the grains due to carrier trapping at the grain boundaries and then tunneling through the grain boundaries is proposed as the carrier transport mechanism. A generalized current-voltage relationship is developed which shows that the electrical properties of polycrystalline silicon depend on the properties of the grain boundaries.

GaAs FET large-signal model and its application to circuit designs

Abstract: A large-signal GaAs FET model is derived based on dc characteristics of the device. Analytical expressions of modeled nonlinear elements are presented in a form convenient for circuit design. Power saturation and gain characteristics of a GaAs FET are studied theoretically and experimentally. An oscillator design employing the large-signal model is demonstrated.

Power-limiting breakdown effects in GaAs MESFET's

Abstract: State-of-the-art GaAs MESFET'S exhibit an output power saturation as the input power is increased Experiments indicated that this power saturation is due to the combined effects of forward gate conduction and reverse gate-to-drain breakdown This reverse breakdown was studied in detail by performing two-dimensional numerical simulations of planar and recessed-gate FET's These simulations demonstrated that the breakdown occurs at the drain-side edge of the gate The results of the numerical simulations suggested a model of the depletion layer configuration which could be solved analytically This model demonstrated that the breakdown voltage was inversely proportional to the product of the doping level and the active layer thickness

Self-aligned bipolar transistors for high-performance and low-power-delay VLSI

Abstract: An n-p-n bipolar transistor structure with the emitter region self-aligned to the polysilicon base contact is described. The self-alignment results in an emitter-to-base contact separation less than 0.4 µm and a collector-to-emitter area ratio about 3:1 for a two-sided base contact. This ratio can be less than 2:1 for a base contacted only on one side. The vertical doping profile can be optimized independently for high-performance and/or high-density and low-power-delay circuit applications. The technology, using recessed oxide isolation, was evaluated using 13-stage nonthreshold logic (NTL) and 11-stage merged-transition logic (MTL) ring-oscillator circuits designed with 2.5 µm design rules. For transistors with 200-nm emitter junction depth the common-emitter current gain for polysilicon emitter contact is typically 2-4 times that for Pd 2 Si emitter contact. There is no observable circuit performance degradation attributable to the polysilicon emitter contact. Typical observed per-stage delays were 190 ps at 1.3 mW and 120 ps at 2.3 mW for the NTL ( FI = FO = 1 ) circuits and 1.3 ns at 0.15 mA for the MTL ( FO = 4 ) circuits.

A temperature model for the GaAs MESFET

Abstract: This paper describes a new two-dimensional method for study of GaAs Schottky-barrier MESFET's. A modified form of the conduction current is used in which transport properties are described in terms of electron temperature rather than electric field. Nonequilibrium velocity effects such as velocity overshoot are included. Results for the one-dimensional GaAs diode and the two-dimensional GaAs MESFET are presented and compared to other studies that utilize the Monte Carlo procedure. Larger values of current cut-off frequency are predicted for submicrometer gate length MESFET's than in previous two-dimensional simulations which utilize the steady-state transport properties.

A retrograde p-well for higher density CMOS

Abstract: A new technique for CMOS p-well (or n-well) formation is described, making use of a deep implant followed by a brief anneal. This results in a retrograde profile, permitting a much shallower well, a large reduction in p-n channel device spacing (5-6 µm versus 10-15 µm), and an opportunity to reduce the risk of latch-up. This technique is more conducive to scaling-with the promise of significantly better performance-than conventional well formation methods. The retrograde p-well has been successfully applied to a linearly shrunk bulk CMOS 4K static RAM, demonstrating its feasibility.

Synthesis of the Pierce gun

Abstract: The design of a Pierce gun is uniquely defined by four parameters: beam voltage, current, waist radius, and cathode current density. The gun convergence angle, cathode spherical radius, anode-cathode spacing, and throw (distance to the waist) are calculated by an iterative procedure which typically converges in four cycles to 0.1°. The anode lens formula of Danielson, Rosenfeld, and Saloom is combined with inverted forms of the Langmuir-Blodgett solution for the spherical diode and the Universal Beam Spread equation for the tunnel region; the iterations match the trajectories at the anode plane. Correction for spherical aberration is made by the method of Frost and Purl as quantified by True. The inverted equations are simple enough to be solved in a few minutes with a programmable calculator. The experimental data of Frost and Purl is used to demonstrate the validity of the procedure for guns of medium perveance.

An experimental wide-band gyrotron traveling-wave amplifier

Abstract: Initial tests of a fast-millimeter-wave wide-band gyrotron traveling-wave amplifier (gyro-TWA)of novel design have demonstrated a small-signal 3-dB bandwidth of 13 percent with 18-dB gain at midband (35 GHz)using a 70-kV 1-A annular electron beam. This reflection-type amplifier using the TE 01 circular-electric mode has a linear tapered Waveguide circuit with an axial magnetic field profiled to maintain synchronism.

Theory of a wide-band distributed gyrotron traveling-wave amplifier

Abstract: We present the concept of an ultra-wide-band distributed gyrotron traveling-wave amplifier for millimeter and submillimeter waves. The radius of the waveguide in the interaction region is increased along the axis, while the strength of the dc magnetic field is decreased in such a way that the wave cutoff frequency is kept nearly equal to the electron cyclotron frequency. The basic principle of operation, peak gain, and saturated efficiency are analyzed. It is shown that instantaneous bandwidth over at least two octaves is theoretical possible. Technological requirements for achieving such an amplifier are assessed, including proposed structures for distributed input wave coupling.

An analytic model for minority-carrier transport in heavily doped regions of silicon devices

Abstract: A simple analytic description of the minority-carrier current injected into typical diffused (or ion-implanted) heavily doped regions of silicon bipolar devices is derived. The effects of energy-bandgap narrowing, majority-carrier degeneracy, Auger recombination, a doping-density gradient, and surface recombination are accounted for tractably by using key approximations. Numerical solutions of the minority-carrier continuity equation support the model and facilitate the evaluation of the model parameters, which follow directly from the doping-density profile. The accuracy of the model is within the bounds of uncertainty emanating from present equivocal characterizations of bandgap narrowing and of Auger carrier lifetimes.

Effects of drift region parameters on the static properties of power LDMOST

Abstract: The effects of the drift region geometry and the physical parameters on the thin layer (resurfed) lateral DMOS transistor operation have been studied for both the static on-state and the off-state. The variations of breakdown voltage with drift region parameters were investigated using numerical modeling and compared to the experimental results. The operation of the LDMOST in the on-channel condition was modeled semi-empirically. The analytical and experimental results show that the operation of the device depends strongly on the geometry and the physical parameters of the drift region, particularly at high gate voltages and low drain voltages. Design guidelines for the lateral DMOS transistor for switching applications are discussed.

N-channel enhancement-mode MOSFET characteristics from 10 to 300 K

Abstract: Operation of MOSFET circuits at the liquid nitrogen temperature (77 K) has been suggested as a means of improving circuit and system performance. Previously reported work emphasizes mobility and threshold voltage at 77 K. However, small MOSFET's require several (≳10) parameters for circuit design. Since a full set of MOSFET model parameters have not been previously reported, it has not been established whether conventional models can be applied for MOSFET circuit design at 77 K. We present here the temperature dependence of a full set of MOSFET circuit model parameters for channel lengths from 2.5 to 8.5 µm and for temperatures ranging from 10 to 300 K. Temperatures below 77 K are of interest in evaluating effects of impurity freezeout and temperatures above 77 K are important since actual device temperatures will be above the ambient. Overall, we find that the mobility and the threshold voltage are the dominant temperature dependent parameters and that conventional I-V characteristics persist down to 77 K. Below 77 K, some new features appear in the I-V characteristics. However, the conventional behavior down to 77 K suggests that standard (circuit models can be used for circuits operating at 77 K. Such circuits would be about four times faster than at room temperature and, with liquid nitrogen cooling, would provide an order of magnitude higher power density for VLSI.

Long-term and instantaneous burnout in GaAs power FET's: Mechanisms and solutions

Abstract: Catastrophic source-drain burnout is an important failure mode in GaAs power FET's. In this paper we show that short-term (instantaneous) and long-term (aging) failures have different physical origins provided the underlying drain ohmic-contact weakness has been suppressed by use of a recessed n+drain ledge geometry. With this drain configuration, instantaneous burnout is due to thermal runaway of the buffer/substrate when local temperatures reach the 500-550°C range. For our typical devices With 30-50-µm-thick substrates, the associated de burnout power is 4-5 W/mm of gate periphery. Long-term aging failure, on the other hand, results from chemical changes at the GaAs surface between gate and drain. These changes induce localized areas of avalanche white-light emission, particularly along the n+ledge, which serve as burnout precursors. A series of aging, surface etching, and passivation experiments has revealed that oxygen probably plays a major role in the aging process, perhaps through its known effect on free arsenic formation. Moreover, it is found that minimization of the oxygen content at the top surface by using si 3 N 4 :H passivation rather than SiO 2 not only prevents white-light emission but increases the median life at 310°C channel temperature from 2.5 to more than 500 h.

Virtual phase technology: A new approach to fabrication of large-area CCD's

Abstract: This article presents a new technology for fabrication of a single-phase CCD. This new technology called virtual phase (VP) employs only a single level gate structure, and is, therefore, ideally suited for fabrication of large-area high-performance devices with high yield, The fundamentals of operation of VP CCD's are discussed, and the advantages and limitations of this new technology are presented. The design, fabrication, and operation of a 490 × 328 TV compatible VP imager is described, and performance parameters as well as imagery are presented.

Monolithic GaAs direct-coupled amplifiers

Abstract: Monolithic GaAs dc-coupled amplifiers with bandwidths up to 5 GHz are described. The multistage amplifiers include designs having 25-dB gain with 2-GHz bandwidth and 10-dB gain with 5-GHz bandwidth. Analysis of gain, bandwidth, and noise agrees with measurements. Distortion mechanisms are discussed, along with the performance of a low-distortion amplifier.

The effect of base doping on the performance of Si bipolar transistors at low temperatures

Abstract: The possibility of using Si bipolar transistors at low temperatures (77 to 200 K) is examined. Estimates of the de-current gain β and the switching performance are obtained from results on the variation of the effective band gap with the concentration of impurities in the emitter region and from the variation of the transport properties with the impurity concentration in the base. The reduction in β at low temperatures cannot be eliminated by using an optimum As concentration in transistors with As doped emitters. There is, however, a significant improvement in the low-temperature from eliminating the compensating acceptors from the emitter region. It is important to also reduce the number of compensating donor traps from the base region at low temperatures. The effect of varying the base doping is calculated using the data on Si of Morin and Maita, replotted to obtain the dependence on impurity concentration. The switching speed goes through a maximum close to 150 K. At even lower temperatures majority-carrier freeze out is responsible for a decreased performance. At low temperatures, the de-current gain can be increased by reducing the base doping. The resulting performance decrease is less than at room temperature and the improvement in β is greater, because, at low temperatures, the decreased impurity scattering at a lighter doping significantly improves the electron and hole mobilities in the base region.

Ballistic electron transport in semiconductors

Abstract: The possibility of ballistic transport in semiconductors is discussed and criteria are given for the experimental verification of ballistic behavior. The potential of purely ballistic motion, velocity overshoot, and inhomogeneities of the free carrier concentration in the space charge limited regime for device performance is assessed.

Charge pumping in SOS—MOS transistors

Abstract: The variation of the floating-substrate potential of SOS-MOS transistors is studied by applying frequent pulses to the gate. The minority carriers are injected into the floating substrate by charge pumping and they recombine there. The injected charges are stored because of the reverse-biased junctions at the source and drain. The threshold-voltage change by the substrate bias is also investigated. If the silicon film is fully depleted under the gate, the threshold-voltage change does not occur. This condition is used to stabilize the high-speed operations of the SOS-MOS integrated circuits. A new memory cell consisting of only one transistor without a storage capacitor is realized utilizing the change of the floating-substrate potential by the charge pumping and the avalanche multiplication. The sensitivity of the memory cell is affected by the channel length of an SOS-MOS transistor. The memory storage time is obtained as 300 µs.

Azide-phenolic resin photoresists for deep UV lithography

Abstract: A photosensitive composition, consisting of an aromatic azide compound (3,3'-diazidodiphenyl sulfone) and a phenolic resin (poly(p-vinylphenol)), called MRS-1, has been prepared and evaluated as a negative deep UV resist for high resolution lithography. Solubility of MRS-1 in an aqueous alkaline developer decreases upon exposure to deep UV radiation. The alkaline developer removes the unexposed areas of MRS-1 by an etching-type development process. No swelling-induced pattern deformation occurs, and images of submicrometer resolution are obtained. The resist is approximately two orders of magnitude more sensitive than PMMA(polymethyl methacrylate). The exposure time of 5 s is sufficient for deep UV contact printing using a 500-W Xe-Hg lamp. The resistance to dry etching of MRS-1 is comparable to that of conventional positive photoresists based on phenolic resin.

A model for conduction in polycrystalline silicon—Part II: Comparison of theory and experiment

Abstract: In the preceding paper [1], a new phenomenological model for the electrical conduction in polycrystalline silicon was developed. Electrical conduction in polycrystalline silicon was shown to be controlled by dopant segregation, carrier trapping, and carrier tunneling through the grain boundaries. In this paper, the theoretical model is compared to experiment. The electrical behavior of polycrystalline silicon is shown to be influenced by the properties of the grain boundaries. In arsenic and phosphorus-doped polycrystalline-silicon films the grain boundaries are best modeled by rectangular barriers with a height of 0.66 eV and an approximate width of 7 A. The width of the grain-boundary barriers and the density of carrier trapping states are found to be weak functions of the dopant species and sample processing. The resistivity is found to be a strong function of dopant concentration, dopant species, and processing history at low and intermediate dopant concentrations, and the model can be used to predict this behavior.

Effect of long-term stress on IGFET degradations due to hot electron trapping

Abstract: The threshold voltage shift through the long-term stress is measured for IGFET's. The gate bias dependence shows that the hot electron trapping is affected strongly by the electric field in the gate insulator. The threshold voltage shift versus time is well explained with the theory modified by the effect of the trapped charge on the subsequent electron trapping. The effect of transistor dimensions and temperature are also discussed.

Optical properties of electrophoretic image displays

Abstract: Those variables determining the optical properties of one type of electrophoretic image display (EPID) are discussed in this paper. The working medium in the EPID with which this paper is concerned is a colloidal suspension of submicron pigment particles in a medium of matching specific gravity and contrasting color. The colloidal suspension is contained between two transparent electrodes. By changing the polarity of the applied voltage, the charged pigment particles may be moved to one or the other electrode. The effects of suspension composition, and the physical and chemical properties of the suspension components are discussed.

Rigid band analysis of heavily doped semiconductor devices

Abstract: The conventional carrier transport equations used in device analysis must be modified for heavily doped semiconductor regions. The modifications to Shoekley's auxiliary equations relating the carrier densities to their corresponding quasi-Fermi levels are derived for the rigid band model. We include the effects of asymmetric bandgap narrowing and of carrier degeneracy (Fermi-Dirac statistics). Emphasis is placed on writing the equations in a simple form that indicates the effect of changes in the band structure due to heavy doping. In this form they can serve as a basis for computer-aided analysis and design. We show that, in general, the effective intrinsic carrier density n ie as well as the electron and hole current densities depend on the asymmetry in bandgap narrowing. However, for the special case of low-level injection, n ie and the minority current density depend only on the total bandgap narrowing \DeltaE_{g} . Furthermore, we indicate that interpretation of experiments with theory using Boltzmann statistics, instead of Femi-Dirac statistics, will underestimate \DeltaE_{g} in degenerate material.

Growth of high-purity semi-insulating bulk GaAs for integrated-circuit applications

Abstract: Growth of high-purity bulk semi-insulating GaAs by the Liquid-Encapsulated Czochralski (LEC) method has produced thermally stable, high-resistivity crystals suitable for use in direct ion implantation. Large round substrates have become available for integrated-circuit processing. The implanted wafers have excellent electrical uniformity (±4 percent V p ) and have shown electron mobility as high as 4800cm2/V.s for Se implants with 1.7 × 1017cm-3peak doping. Careful control of background doping through in situ synthesis has produced GaAs with Si concentrations as low as 6 × 1014cm-3grown from SiO 2 crucibles. Detailed results of qualification tests for ion implantation in LEC GaAs will be discussed. Feasibility of successful high-speed GaAs large-scale integrated circuits using LEC substrates will be described.

A functional GaAs FET noise model

Abstract: It is the purpose of this paper to develop a theory upon which the design of low noise FET amplifiers can be based. This is not a fundamenta model of the noise mechanisms in GaAs FET's, but rather, an endeavor to relate physically measurable device capacitances and resistances to the device noise figure and optimum noise source impedance. I will be shown that the noise performance of an FET can be adequately described by two uncorrelated noise sources. One, at the input of the FET, is the thermal noise generated in the various resis, tances in the gate-source loop. This noise source is frequency dependent and it can be calculated from the equivalent circuit of the FET. The second noise source, in the Output of the FET, is frequency independent, and not recognizably related to any measured parameters. This output nise is a function of drain current and voltage. The decomposition of the FET noise into two uncorrelated sources simplifies the design of broad-band low noise amplifiers. Once the equivalent circuit of a device and its noise figure at one frequency are known, the optimum noise source impedance and noise figure over a broad range of frequencies may be calculated. For the device designer this model also may be helpful in balancing input-output noise tradeoffs.