This paper focuses on approaches to continuing CMOS scaling by introducing new device structures and new materials. Starting from an analysis of the sources of improvements in device performance, we present technology options for achieving these performance enhancements. These options include high-dielectric-constant (high-k) gate dielectric, metal gate electrode, double-gate FET, and strained-silicon FET. Nanotechnology is examined in the context of continuing the progress in electronic systems enabled by silicon microelectronics technology. The carbon nanotube field-effect transistor is examined as an example of the evaluation process required to identify suitable nanotechnologies for such purposes.

Beyond the conventional transistor

Total ionizing dose radiation effects on the electrical properties of metal-oxide-semiconductor devices and integrated circuits are complex in nature and have changed much during decades of device evolution. These effects are caused by radiation-induced charge buildup in oxide and interfacial regions. This paper presents an overview of these radiation-induced effects, their dependencies, and the many different approaches to their mitigation.

Radiation effects and hardening of MOS technology: devices and circuits

Silicon-based CMOS technology can be scaled well into the nanometer regime. High-performance, planar, ultrathin-body devices fabricated on silicon-on-insulator substrates have been demonstrated down to 15-nm gate lengths. We have also introduced the FinFET, a double-gate device structure that is relatively simple to fabricate and can be scaled to gate lengths below 10 nm. In this paper, some of the key elements of these technologies are described, including sublithographic patterning, the effects of crystal orientation and roughness on carrier mobility, gate work function engineering, circuit performance, and sensitivity to process-induced variations.

Extremely scaled silicon nano-CMOS devices

In this paper, we explore the scaling limits of alternative gate dielectrics based on their direct-tunneling characteristics and gate-leakage requirements for future CMOS technology generations. Important material parameters such as the tunneling effective mass are extracted from the direct-tunneling characteristics of several promising high-/spl kappa/ gate dielectrics for the first time. We also introduce a figure-of-merit for comparing the relative advantages of various gate dielectrics based on the gate-leakage current. Using an accurate direct-tunneling gate-current model and specifications from the International Technology Roadmap for Semiconductors (ITRS), we provide guidelines for the selection of gate dielectrics to satisfy the projected off-state leakage current requirements of future high-performance and low-power technologies.

MOSFET gate leakage modeling and selection guide for alternative gate dielectrics based on leakage considerations

Nitrogen implantation of Mo gate was used to fabricate MOS capacitors and CMOS transistors. Initial studies demonstrate that the work function of Mo is sensitive to nitrogen implantation energy. Mo with (110) orientation exhibits a high work function, making it suitable for bulk p-MOSFET gate electrodes. Nitrogen implantation can be used to lower the Mo work function, making it suitable for n-MOSFET gate electrodes. A gate work function reduction of 0.42 eV was achieved for the n-FETs on CMOS wafers. With further optimization, this single metal gate technology may potentially replace conventional poly-Si gate technology for CMOS and can also be used for multiple-VTtechnologies.

An adjustable work function technology using Mo gate for CMOS devices

CMOS transistors were fabricated using a single metal, [110]-Mo, as the gate material [110]-Mo shows a high work function value that is suitable for PMOSFETs, and, with nitrogen implantation, its work function can be reduced to meet the requirements of NMOSFETs The change in Mo work function can be controlled by the nitrogen implant parameters, which is potentially useful for multiple-V/sub T/ technology TEM and EDS analysis show that Mo gate electrodes are stable after undergoing a conventional CMOS process

https://www.vlsisymposium.org/Past/01web/technology/tec_pdf/T5Ap1.pdf

Metal gate work function adjustment for future CMOS technology

We explore the dependence of metal and polysilicon gate work functions on the underlying gate dielectric in advanced MOS transistors. The interface dipole theory is employed to explain our experimental observation that metal work functions on high-/spl kappa/ dielectrics differ appreciably from their values on SiO/sub 2/ or in vacuum. This model shows excellent agreement with original data and reported results in the literature. In addition, we also explain the weaker dependence of n/sup +/ and p/sup +/ polysilicon gate work functions on the gate dielectric. Challenges for gate work function engineering are highlighted. This work provides additional guidelines on the choice of gate materials for future CMOS technology incorporating high-/spl kappa/ gate dielectrics.

Effects of high-/spl kappa/ dielectrics on the workfunctions of metal and silicon gates

Mo metal gate p-MOSFETs with several advanced gate dielectrics were fabricated A suitable p-MOSFET work function was achieved and good device characteristics were obtained in all cases Thermodynamic stability of Mo on Si/sub 3/N/sub 4/, ZrO/sub 2/ and ZrSiO/sub 4/ was verified by good carrier mobility agreement with the universal mobility model

Molybdenum metal gate MOS technology for post-SiO/sub 2/ gate dielectrics

The hot carrier reliability of n-channel MOSFETs with 11 /spl Aring/ EOT HfO/sub 2/ gate dielectric and poly-Si gates was studied. Under peak I/sub SUB/ stress conditions, n-FETs with HfO/sub 2/ gate dielectric show longer lifetime when compared to SiO/sub 2/ n-FETs for the same stress substrate current. At room temperature, the 0.15 /spl mu/m channel length HfO/sub 2/ n-FETs are projected to have a 10-year lifetime at V/sub D/ = 2.76 V.

R. Lin

Papers

An adjustable work function technology using Mo gate for CMOS devices

Metal gate work function adjustment for future CMOS technology

Effects of high-/spl kappa/ dielectrics on the workfunctions of metal and silicon gates

Molybdenum metal gate MOS technology for post-SiO/sub 2/ gate dielectrics

Hot carrier reliability of n-MOSFET with ultra-thin HfO/sub 2/ gate dielectric and poly-Si gate