This paper considers the design, fabrication, and characterization of very small Mosfet switching devices suitable for digital integrated circuits, using dimensions of the order of 1 /spl mu/. Scaling relationships are presented which show how a conventional MOSFET can be reduced in size. An improved small device structure is presented that uses ion implantation, to provide shallow source and drain regions and a nonuniform substrate doping profile. One-dimensional models are used to predict the substrate doping profile and the corresponding threshold voltage versus source voltage characteristic. A two-dimensional current transport model is used to predict the relative degree of short-channel effects for different device parameter combinations. Polysilicon-gate MOSFET's with channel lengths as short as 0.5 /spl mu/ were fabricated, and the device characteristics measured and compared with predicted values. The performance improvement expected from using these very small devices in highly miniaturized integrated circuits is projected.

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Design of ion-implanted MOSFET's with very small physical dimensions

A simple model describing the DC behavior of MOS transistors operating in weak inversion is derived on the basis of previous publications. This model includes only two parameters and is suitable for circuit design. It is verified experimentally for both p- and n-channel test transistors of a Si-gate low-voltage CMOS technology. Various circuit configurations taking advantage of weak inversion operation are described and analyzed: two different current references based on known bipolar circuits, an amplitude detector scheme which is then applied to a quartz oscillator with the result of a very low-power consumption (<0.1 /spl mu/W at 32 kHz), and a low-frequency bandpass amplifier. All these circuits are insensitive to threshold and mobility variations, and compatible with a CMOS technology dedicated to digital low-power circuits.

CMOS analog integrated circuits based on weak inversion operations

The aim of this paper is to give a thorough overview of flash memory cells. Basic operations and charge-injection mechanisms that are most commonly used in actual flash memory cells are reviewed to provide an understanding of the underlying physics and principles in order to appreciate the large number of device structures, processing technologies, and circuit designs presented in the literature. New cell structures and architectural solutions have been surveyed to highlight the evolution of the flash memory technology, oriented to both reducing cell size and upgrading product functions. The subject is of extreme interest: new concepts involving new materials, structures, principles, or applications are being continuously introduced. The worldwide semiconductor memory market seems ready to accept many new applications in fields that are not specific to traditional nonvolatile memories.

Flash memory cells-an overview

The Berkeley short-channel IGFET model (BSIM), an accurate and computationally efficient MOS transistor model, and its associated characterization facility for advanced integrated-circuit design are described. Both the strong-inversion and weak-inversion components of the drain current expression are included. In order to speed up the circuit-simulation execution time, the dependence of the drain current on the substrate bias has been modeled with a numerical approximation. This approximation also simplifies the transistor terminal-charge expressions. The charge model was derived from its drain-current counterpart to preserve consistency of device physics. Charge conservation is guaranteed in this model.

BSIM: Berkeley short-channel IGFET model for MOS transistors

Flexible non-volatile memories have attracted tremendous attentions for data storage for future electronics application. From device perspective, the advantages of flexible memory devices include thin, lightweight, printable, foldable and stretchable. The flash memories, resistive random access memories (RRAM) and ferroelectric random access memory/ferroelectric field-effect transistor memories (FeRAM/FeFET) are considered as promising candidates for next generation non-volatile memory device. Here, we review the general background knowledge on device structure, working principle, materials, challenges and recent progress with the emphasis on the flexibility of above three categories of non-volatile memories.

Towards the development of flexible non-volatile memories.

A knowledge of subthreshold behavior in an insulated gate field-effect transistor is important for circuits with low leakage specifications. This paper discusses the effect of drain voltage on the subthreshold region as the channel length becomes shorter, the effect of substrate bias on both the shift in and the slope of the subthreshold curves, and the effect of temperature on the subthreshold current characteristics. It is shown that all these effects can be incorporated into a simple one-dimensional model.

Subthreshold design considerations for insulated gate field-effect transistors

The authors discuss the emission of both substrate and channel hot electrons from the silicon into the gate insulator of n-channel IGFETs. In each case the discussion begins with a physical model to elucidate the many parametric dependencies. The effect of changing important material and geometrical parameters as well as temperature and terminal voltages is documented with emission data. Under proper conditions the majority of emitted hot electrons are collected at the gate electrode, so that electron heating can be studied by directly observing gate current. In addition, gate current is a sensitive probe of trapping effects in the gate insulator, and it is shown how these measurements can be used to deduce long-term stability in IGFET structures.

R.R. Troutman

Papers

Subthreshold design considerations for insulated gate field-effect transistors

Hot-electron emission in n-channel IGFETs