R
R. Ranica
Researcher at STMicroelectronics
Publications - 38
Citations - 852
R. Ranica is an academic researcher from STMicroelectronics. The author has contributed to research in topics: Transistor & CMOS. The author has an hindex of 14, co-authored 37 publications receiving 805 citations. Previous affiliations of R. Ranica include Commissariat à l'énergie atomique et aux énergies alternatives.
Papers
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Proceedings ArticleDOI
A one transistor cell on bulk substrate (1T-Bulk) for low-cost and high density eDRAM
R. Ranica,Alexandre Villaret,Pierre Malinge,Pascale Mazoyer,Damien Lenoble,Philippe Candelier,Francois Jacquet,Pascal Masson,R. Bouchakour,Richard Fournel,J.P. Schoellkopf,Thomas Skotnicki +11 more
TL;DR: In this article, a 1T cell for high-density eDRAM has been successfully developed on bulk silicon substrate for the first time, and the integration of the memory cell in a matrix arrangement is evaluated.
Proceedings ArticleDOI
A capacitor-less DRAM cell on 75nm gate length, 16nm thin fully depleted SOI device for high density embedded memories
R. Ranica,Alexandre Villaret,Claire Fenouillet-Beranger,Pierre Malinge,Pascale Mazoyer,Pascal Masson,D. Delille,Clement Charbuillet,Philippe Candelier,Thomas Skotnicki +9 more
TL;DR: In this article, a capacitor-less DRAM cell on very thin film (Tsi=16nm) and short gate length (Lg=75nm) was demonstrated for the first time.
Journal ArticleDOI
Mechanisms of charge modulation in the floating body of triple-well nMOSFET capacitor-less DRAMs
Alexandre Villaret,R. Ranica,Pascal Masson,Pierre Malinge,Pascale Mazoyer,Philippe Candelier,Francois Jacquet,Sorin Cristoloveanu,Thomas Skotnicki +8 more
TL;DR: In this paper, the authors report on the modeling and characterization of the memory effect observed on triple-well nMOSFETs and compare the modeled and measured data at room temperature.
Journal ArticleDOI
Further insight into the physics and modeling of floating-body capacitorless DRAMs
Alexandre Villaret,R. Ranica,Pierre Malinge,Pascal Masson,B. Martinet,Pascale Mazoyer,Philippe Candelier,Thomas Skotnicki +7 more
TL;DR: In this article, the authors report on parasitic bipolar conduction occurring in floating-body effect based capacitor-less DRAMs, and a way to include these effects into a previously developed model is presented.
Proceedings ArticleDOI
Scaled IT-Bulk devices built with CMOS 90nm technology for low-cost eDRAM applications
R. Ranica,Alexandre Villaret,Pierre Malinge,G. Gasiot,Pascale Mazoyer,P. Roche,Philippe Candelier,Francois Jacquet,Pascal Masson,R. Bouchakour,Richard Fournel,J.P. Schoellkopf,Thomas Skotnicki +12 more
TL;DR: In this article, a one transistor DRAM cell realized on bulk substrate (lT-Bulk) with CMOS 90nm platform is presented for the first time, which is fully compatible with logic process integration and includes only few additional steps.