Technology scaling has entered a new era, where chip performance is constrained by power dissipation. Power limits vary with the application domain; however, they dictate the choices of technology and architecture and necessitate implementation techniques that tradeoff performance for power savings. This paper examines technology options in the power-limited-scaling regime and reviews sensitivity-based analysis that can be used for the optimal selection of optimal architectures and circuit implementations to achieve the best performance under power constraints. These tradeoffs are examined in the context of power minimization at the technology, circuit, logic, and architecture levels, both at the design and run times.

Design in the Power-Limited Scaling Regime

In this paper, we present a carry skip adder (CSKA) structure that has a higher speed yet lower energy consumption compared with the conventional one. The speed enhancement is achieved by applying concatenation and incrementation schemes to improve the efficiency of the conventional CSKA (Conv-CSKA) structure. In addition, instead of utilizing multiplexer logic, the proposed structure makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) compound gates for the skip logic. The structure may be realized with both fixed stage size and variable stage size styles, wherein the latter further improves the speed and energy parameters of the adder. Finally, a hybrid variable latency extension of the proposed structure, which lowers the power consumption without considerably impacting the speed, is presented. This extension utilizes a modified parallel structure for increasing the slack time, and hence, enabling further voltage reduction. The proposed structures are assessed by comparing their speed, power, and energy parameters with those of other adders using a 45-nm static CMOS technology for a wide range of supply voltages. The results that are obtained using HSPICE simulations reveal, on average, 44% and 38% improvements in the delay and energy, respectively, compared with those of the Conv-CSKA. In addition, the power–delay product was the lowest among the structures considered in this paper, while its energy–delay product was almost the same as that of the Kogge–Stone parallel prefix adder with considerably smaller area and power consumption. Simulations on the proposed hybrid variable latency CSKA reveal reduction in the power consumption compared with the latest works in this field while having a reasonably high speed.

High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

Energy-efficient design requires exploration of available algorithms, recurrence structures, energy and wire tradeoffs, circuit design techniques, circuit sizing and system constraints. In this paper, methodology for energy-efficient design applied to 64-bit adders implemented with static CMOS, dynamic CMOS and CMOS compound domino logic families, is presented. We also examined 65 nm, 45 nm, 32 nm, and 22 nm technology nodes to explore the applicability of the results in deep submicron technologies. By applying energy-delay tradeoffs on various levels, we developed adder topology yielding up to 20% performance improvement and 4.5× energy reduction over existing designs.

Energy-Efficient Design Methodologies: High-Performance VLSI Adders

The reduction in the operating voltage play a majorrole in improving the performance of the integratedcircuits.Apart from that lesser power consumption, reducedarea and smaller size of transistors are also the vital factors inthe design criteria and fabrication of the systems. This articleapproaches towards the increasing performance of the systemsby comparing different types of adder circuits. In this article, anew circuit has been designed using the TG technology. Basedon different parameters like average power consumption anddelay, it has been observed that the Carry look-ahead adderand Carry bypass adder consumes more power. TheComparative analysis of TG based 8-bit different AdderDesigns using 180nm technology using TANNER tool has beenconsidered.

Analysis and Comparison: Full Adder Block in Submicron Technology

Exploration of energy efficient design methodologies: High performance VLSI adders

A methodology for energy-delay optimization of digital circuits is presented. This methodology is applied to minimizing the delay of representative carry-lookahead adders under energy constraints. Impact of various design choices, including the carry-lookahead tree structure and logic style, are analyzed in the energy-delay space and verified through optimization. The result of the optimization is demonstrated on a design of the fastest adder found, a 240-ps Ling sparse domino adder in 1 V, 90 nm CMOS. The optimality of the results is assessed against the impact of technology scaling.

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R. Zlatanovici

Papers

Energy–Delay Optimization of 64-Bit Carry-Lookahead Adders With a 240 ps 90 nm CMOS Design Example