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Design Of Analog Cmos Integrated Circuits

Ingestible electronics have revolutionized the standard of care for a variety of health conditions. Extending the capacity and safety of these devices, and reducing the costs of powering them, could enable broad deployment of prolonged monitoring systems for patients. Although prior biocompatible power harvesting systems for in vivo use have demonstrated short minute-long bursts of power from the stomach, not much is known about the capacity to power electronics in the longer term and throughout the gastrointestinal tract. Here, we report the design and operation of an energy-harvesting galvanic cell for continuous in vivo temperature sensing and wireless communication. The device delivered an average power of 0.23 μW per mm2 of electrode area for an average of 6.1 days of temperature measurements in the gastrointestinal tract of pigs. This power-harvesting cell has the capacity to provide power for prolonged periods of time to the next generation of ingestible electronic devices located in the gastrointestinal tract.

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Prolonged energy harvesting for ingestible devices.

A latch-type comparator with a dynamic bias pre-amplifier is implemented in a 65-nm CMOS process. The dynamic bias with a tail capacitor is simple to implement and ensures that the pre-amplifier output nodes are only partially discharged to reduce the energy consumption. The comparator is analyzed and compared to its prior art in terms of energy consumption and input referred noise voltage. First-order equations are presented that show how to optimize the pre-amplifier for low noise and high gain. Both the dynamic bias comparator and the prior art are implemented on the same die and measurements show that the dynamic bias can reduce the average energy consumption by about a factor 2.5 for the same input-equivalent noise at an input common-mode level of half the supply voltage.

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A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise

This paper presents an inductive DC-DC boost converter for energy harvesting using a thermoelectric generator with a minimum startup voltage of 70 mV and a regulated output voltage of 1.25 V. With a typical generator resistance of $40~\Omega $ , an output power of $17~ {\mu }\text{W}$ can be provided, which translates to an end-to-end efficiency of 58%. The converter employs Schmitt-trigger logic startup control circuitry and an ultra-low voltage charge pump using modified Schmitt-trigger driving circuits optimized for driving capacitive loads. Together with a novel ultra-low leakage power switch and the required control scheme, to the best of the authors’ knowledge, this enables the lowest minimum voltage with fully integrated startup.

Fully Integrated Startup at 70 mV of Boost Converters for Thermoelectric Energy Harvesting

An ultra-low power electrocardiogram (ECG) processing architecture with an adequate level of accuracy is a necessity for Internet of Things (IoT) medical wearable devices. This paper presents a novel real-time QRS detector and an ECG compression architecture for IoT healthcare devices. An absolute-value curve length transform (A-CLT) is proposed that effectively enhances the QRS complex detection with minimized hardware resources. The proposed architecture requires adders, shifters, and comparators only, and removes the need for any multipliers. QRS detection was accomplished by using adaptive thresholds in the A-CLT transformed ECG signal, and achieved a sensitivity of 99.37% and the predictivity of 99.38% when validated using Physionet ECG database. Furthermore, a lossless compression technique was incorporated into the proposed architecture that uses the ECG signal first derivative and entropy encoding. An average compression ratio of 2.05 was achieved when evaluated using MIT-BIH database. The proposed QRS detection architecture deals with almost all the ECG signal artifacts, such as low-frequency noise, baseline drift, and high-frequency interference with minimum hardware resources. The proposed QRS architecture was synthesized using 65-nm low-power process using standard-cell-based flow. The power consumption of the design was 6.5 nW while operating at a supply of 1 V and a frequency of 250 Hz. Moreover, the system could benefit from duty-cycling.

Ultra-Low Power QRS Detection and ECG Compression Architecture for IoT Healthcare Devices

Miniature $\text{mm}^3$ -sized sensor nodes have a very tight power budget, in particular, when a long operational lifetime is required, which is the case, e.g., for implantable devices or unobtrusive IoT nodes. This paper presents a fully integrated signal acquisition IC for these emerging applications. It integrates an amplifier with 32 dB gain and 370 Hz bandwidth that includes positive feedback to enhance input impedance and dc offset compensation. The IC includes also a 10 bit 1 kS/s SAR ADC as well as a clock generator and voltage and current biasing circuits. The overall system achieves an input noise of $27\;\upmu \text {V}_{{\text{rms}}}$ , consumes 3 nW from a 0.6 V supply, occupies $0.20\;\text {mm}^2$ in 65 nm CMOS, and has a single-wire data interface. The amplifier achieves an noise-efficiency factor (NEF) of 2.1 and the ADC has a figure-of-merit (FoM) of 1.5 fJ/conversion-step. Measurements confirm reliable operation for supplies from 0.50 to 0.70 V and temperatures in the range of 0–85 °C. As an application example, an ECG recording is successfully performed with the system while a $0.69\; \text{mm}^2$ photodiode array provides its power supply in indoor lighting conditions.

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A 0.20 $\text {mm}^2$ 3 nW Signal Acquisition IC for Miniature Sensor Nodes in 65 nm CMOS

Signal acquisition systems for emerging applications, such as impiantatile or unobtrusively wearable autonomous sensors, large sensor arrays, or wireless self-powered sensors, require a minuscule form factor and very low power consumption. For example, the power available from a state-of-the-art 1mm3 solid-state thin-film battery is limited to 4nWfora 10yr lifetime [1], and a 1mm3 energy harvester attached to a running person delivers only 7.4nW [2]. While several low-power signal acquisition systems have been proposed [3-5], their consumption is still in the 20-to-1000nW range. Circuits aiming at low absolute power often result in low power-efficiency (due to overhead), high PVT sensitivity and poor reliability (due to the use of simplistic circuitry). This work presents a fully-integrated signal acquisition IC with six-fold lower power consumption than prior art, which provides state-of-the-art power-efficiency and ensures enough circuit reliability, precision and bandwidth to enable practical applications.

21.2 A 3nW signal-acquisition IC integrating an amplifier with 2.1 NEF and a 1.5fJ/conv-step ADC

This paper presents a 10 b 80 kS/s SAR ADC with low-power duty-cycled reference generation. It generates a stable reference voltage on chip for the SAR ADC and imparts very good immunity against power supply interference to the ADC. A 0.62 V-VDD 25 nW CMOS reference voltage generator (RVG) is presented, which has only ±1.5% variation over process corners. A duty-cycling technique is applied to enable 10% duty-cycling of the RVG, resulting in negligible power consumption of the RVG compared to that of the ADC. Furthermore, a bi-directional dynamic preamplifier is adopted in the SAR ADC, which consumes about half the power compared with a regular dynamic structure and maintains noise and gain performance. Compared with prior-art low-power ADCs, this work is the first to integrate the reference generation and include it in the power consumption while maintaining a competitive 2.4 fJ/conversion-step FoM. The chip is fabricated in 65 nm CMOS technology.

A106nW 10 b 80 kS/s SAR ADC With Duty-Cycled Reference Generation in 65 nm CMOS

Autonomous wireless sensor nodes need low-power low-speed ADCs to digitize the sensed signal. State-of-art SAR ADCs can accomplish this goal with high power-efficiency (<10fJ/conversion-step) [1-4]. The reference voltage design is critical for the ADC performance to obtain good PSRR, low line-sensitivity and a stable supply-independent full-scale range. However, solutions for efficient reference voltage generators (RVGs) are typically ignored in low-power ADC publications. In reality, due to the low power supply (usually sub-1 V) and limited available power (nW-range), the RVG is a challenge within the sensor system. In this work, a 2.4fJ/conversion-step SAR ADC with integrated reference is implemented. The 0.62V CMOS RVG consumes 25nW. To further reduce RVG power, it can be duty-cycled down to 10% with no loss in ADC performance. Additionally, the ADC uses a bidirectional dynamic comparator to improve the power efficiency even more.

15.4 A 0.8V 10b 80kS/s SAR ADC with duty-cycled reference generation

This paper presents the design and measurement of a low noise variable gain amplifier (VGA) over the frequency band of 57 GHz and 64 GHz, using 40-nm CMOS technology. The design applies an inductive degeneration technique for simultaneously noise and power matching, a layout gate inductance for gain frequency extension, and current steering technique for gain tuning. The comparison of a low noise amplifier (LNA) and a low noise VGA is done, in terms of noise figure and linearity (IIP3). The LNA achieves 6.7 dB gain and 4.3 dB noise figure (NF) at 60 GHz, while consuming 12 mA from a 1.1 V supply. The IIP3 of the LNA is −12.8 dBm. The VGA has an S 21 of 6.67 dB (maximum) and 5.1 dB NF at 58 GHz. The gain tuning range is 6 dB and the NF deviation is 0.8 dB at 60 GHz and the IIP3 is −7.66 dBm at the maximum gain state. The supply voltage of the VGA is 1.1 V and the DC current is 11 mA.

Rainier van Dommele

Papers

A 0.20 $\text {mm}^2$ 3 nW Signal Acquisition IC for Miniature Sensor Nodes in 65 nm CMOS

21.2 A 3nW signal-acquisition IC integrating an amplifier with 2.1 NEF and a 1.5fJ/conv-step ADC

A106nW 10 b 80 kS/s SAR ADC With Duty-Cycled Reference Generation in 65 nm CMOS

15.4 A 0.8V 10b 80kS/s SAR ADC with duty-cycled reference generation

A 60 GHz low noise variable gain amplifier with small noise figure and IIP3 variation in a 40-nm CMOS technology