Showing papers by "Rajiv V. Joshi published in 1995"

Soft metal conductor and method of making

Abstract: A soft metal conductor for use in a semiconductor device which has an uppermost layer consisting of grains having grain sizes sufficiently large so as to provide a substantially scratch-free surface upon polishing in a subsequent polishing step. The invention also provides a method for making a soft metal conductor that has a substantially scratch-free surface upon polishing by a multi-step deposition process, i.e., first sputtering at a higher temperature and then sputtering at a lower temperature and followed by another high temperature sputtering process. The invention further discloses a method for forming a substantially scratch-free surface on a soft metal conductor by first depositing a soft metal layer at a low deposition temperature and then annealing the soft metal layer at a higher temperature to increase the grain size of the metal. The invention also discloses a dual-step deposition method for making a soft metal conductor for use in an electronic device by first depositing a first layer of metal by a physical vapor deposition technique to a first thickness, and then depositing a second layer of metal on top of the first layer of metal to a second thickness larger than the first thickness by a method of chemical vapor deposition, electroplating or electroless plating. The first deposition process may further be conducted by a chemical vapor deposition technique, with the second deposition process conducted by a physical vapor deposition technique.

A highly reliable low temperature Al-Cu line/via metallization for sub-half micrometer CMOS

Abstract: In this paper we present significant advances over the current art in terms of enhanced electromigration lifetime, low temperature deposition, and improved damascene capability of Al-Cu via/line structure. The electromigration data shows that Al-Cu via/interconnect structure deposited by a new low pressure sputtering process (LPS) results in at least "9/spl times/" better electromigration lifetime (t/sub 50/) to that of conventionally used CVD W stud/Al-Cu interconnect structure. This significant improvement in the reliability may be attributed to the "breakthrough" in void-free filling of high aspect ratio (3 to 4) sub-half micrometer vias with low resistivity metal such as Al-Cu at as low temperature as room temperature. The LPS process eliminates the need of a collimator normally used to fill or coat the vias and improves throughput by a factor of 5/spl times/ at least compared to collimation. The extendibility of this technique beyond 0.25 /spl mu/m contact geometries is demonstrated. The integration of the LPS process, Al-Cu via/interconnects using damascene process demonstrates a working 512 K SRAM chip with 0.5 /spl mu/m minimum groundrules.

Formation of Al‐Cu via/interconnect by low‐pressure collimated sputtering

Abstract: This paper describes the effect of low‐pressure collimated sputtering (LPCS) on deposition rates, step coverages, and electrical properties of Al‐Cu. The LPCS deposition is achieved in a magnetron sputter deposition system with a hollow cathode and collimator. The deposition results show that as the via or line size reduces, a complete fill requires a monotonic increase in the aspect ratio of the collimator which limits the throughput for a thick deposition, especially at high pressures (≳1 mT). The benefit of the LPCS is the improved deposition rate (scaled to power) of 1.5–2× compared to the conventional high‐pressure collimated deposition. The integration of LPCS process to fabricate a two‐level Al‐Cu metal structure with submicron Al‐Cu studs (aspect ratio of 2) shows excellent via and electromigration resistances.

Reset and pulse width control circuits for high-performance multi-port memories and register files

Abstract: A single sequential timing chain provides inadequate precision of reset-pulse timing and inadequate reset-pulsewidth control for high-performance memories or register files incorporating dynamic circuits. Also, in such circuits, an inevitable lengthening of pulses, from input to output, ensues. These shortcomings are eliminated by the disclosed multiple-branch circuits, which provide for the generation of appropriate control pulses, and by employment of evaluation-path pulsewidth-shortening circuits appropriately interconnected to the control-generation circuits.

Low temperature, low resistivity sub-half micron via/interconnect structure using reaction of Al-alloys and germane

Abstract: This paper presents a novel, low cost, low temperature process for filling high aspect ratio vias/lines with Al-based alloys with improved damascene capability. This is achieved by reacting Germane (GeH/sub 4/) at temperatures below 400/spl deg/C with Al-Cu alloys deposited by conventional techniques which result in voids, gaps and poor filling. The technique practically imposes no limitation on filling high aspect ratio vias including undercuts. The low temperature provides capability to form multilevel homogeneous Al-alloy via/line structure by maintaining the resistance of underlying interconnects. The reliability data shows that Al-Cu-Ge via/interconnect structure deposited by this method is at least "1.5/spl times/" better electromigration life time (t/sub 50/) to that of hot sputtered Al-Cu (deposited at 535/spl deg/C) and almost "1.8/spl times/" to that of conventionally used CVD W stud/Al-Cu interconnect structure. The improvement in the reliability may be attributed to filling without voids high aspect ratio sub-half micron vias with low resistivity metal such as Al-Cu-Ge at temperatures well below 400/spl deg/C. A lower sheet resistance of Al-Cu-Ge line is achieved by this method compared to high temperature deposition due to less Ti wetting layer and limited Titanium reaction with Al-Cu-Ge. The other important result is that it is possible to achieve "high via chain yields" of difficult to polish materials like Al-alloys using a "unique" polishing process.

Method of forming a damascene structure with WGe polishing stop

Abstract: of EP0915501A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys deposited in high aspect ratio structures including lines and vias. By using a germanium gas flow, germanium (Ge) will be introduced in a surface reaction which prevents voids and side seams and which also provides a passivating layer of CuGe. If a hard cap is needed for surface passivation or a wear-resistance application, the GeH4 gas followed by WF6 can be used to produce an in-situ hard cap of WxGey. Further, high aspect ratio vias/lines (aspect ratio of 3 or more) can be filled by utilizing low pressures and high temperatures (i.e., below 450 DEG C) without degrading the underlying metals.