A Design Methodology to Optimize the Device Performance in CNTFET

The carbon nanotube field-effect transistor (CNFET) is emerging as one of the most promising alternatives to complementary metal---oxide---semiconductor (CMOS) transistors due to its one-dimensional (1-D) band structure, low off-current capability, near-ballistic transport operation, high stability, and low power consumption. This paper presents the design of a CNFET-based ternary content-addressable memory (TCAM) cell and rigorously analyzes its performance in terms of power---delay product (PDP) and static noise margin (SNM). The effect of variations of the chiral vector on the performance of the TCAM cell is also comprehensively investigated. While selecting the chirality, SNM, PDP, and search time are considered as figures of merit. In this TCAM cell design, we apply the same chirality for all CNFETs of the same type. Extensive HSPICE simulations have been performed for computation of performance parameters using the Stanford University CNFET model. Comparison of CNFET- and CMOS-based TCAM cells has been carried out at the 16-nm technology node. The results show that the CNFET-based TCAM cell exhibits significant improvements of PDP, i.e., by 38 % during write operation and 98 % during search operation, and 53 % in SNM, compared with its CMOS counterpart. It is also observed that the best chirality for the TCAM cell design is (22, 19, 0) or (10, 19, 0) from the point of view of SNM and PDP, respectively.

Design and performance analysis of a CNFET-based TCAM cell with dual-chirality selection

The limitation of CMOS to operate under 25nm is a major concern, which is viewed in this paper. Also, scaling issues like leakage current, lower carrier mobility, higher junction capacitance limits the transistor operation is discussed. At lower voltage values, CMOS productive decreases drastically, which reflects on the performance of the circuit to achieve its criteria’s. In the present-day scenario of electronic industry, the speed of the processor is increasing, the urge for speed cache memory is also increasing. In cache memory design, SRAM cell is mainly used, CMOS SRAM Cells are producing more delay and also limitations like mentioned above. Therefore, an alternative preferred choice for SRAM Cells is FinFET, which increases the speed of the Cell by avoiding limitations caused by the bulk CMOS. By considering the advantages of the FinFET, SRAM Cells are implemented in Cadence virtuoso using FinFET 18nm Spectre. In this paper, standard SRAM Cells like 7T, 8T, 9T, and 1oT are simulated and parameters like power, delay, power delay product (PDP), energy-delay product (EDP) are calculated and respective values are presented by varying the voltage (V). SRAM Cells behavior under different voltages is graphically represented. CMOS SRAM Cell values have been taken from previous works of SRAM. By comparing the parameters, a drastic increase in the speed of the FinFET SRAM Cells can be observed over CMOS SRAM Cells.

Comparative Validation of SRAM Cells Designed using 18nm FinFET for Memory Storing Applications

Q-factor is a reasonable index to investigate the integrity of circuits or devices in terms of their energy or charge storage capabilities. We use this figure of merit to explore the deposition quality of nano-node high-k gate dielectrics by decoupled-plasma nitridation at different temperatures with a fixed nitrogen concentration. This is very important in radio-frequency applications. From the point of view of the Q-factor, the device treated at a higher annealing temperature clearly demonstrates a better Q-factor value. Another interesting observation is the appearance of two troughs in the Q-VGS characteristics, which are strongly related to either the series parasitic capacitance, the tunneling effect, or both.

Q-Factor Performance of 28 nm-Node High-K Gate Dielectric under DPN Treatment at Different Annealing Temperatures


 This paper demonstrates the impact of temperature variation on vertically stacked junctionless nanosheet field effect transistor (JL-NSFET) concerning analog/RF performances using different gate lengths (Lg) along with high-k gate dielectrics. A comprehensive analysis of analog/RF performances like transconductance (gm), gate capacitance (Cgg), gate to drain capacitance (Cgd), output conductance (gds), intrinsic gain (Av), maximum oscillation frequency (fMAX), gain frequency product (GFP), and cutoff frequency (fT) is carried out for the temperature range 77-400 K. Note that with the decrease in temperature from 400 to 77 K, there is an improvement in AV, GFP, fT, and fMAX by ~7.43%, ~78.4%, ~78.38%, ~50.9%, respectively. It is also found AV gets degraded with the downscaling of Lg from 16 to 8 nm. However, the same resulted in the improvement of RF performance. From detailed analysis, it is further observed that the usage of high-k gate dielectrics (k=22) in JL-NSFET devices is not suitable due to the depreciation of analog/RF FOMs. Moreover, it is also noted that the improvement in analog/RF performance (ΔFoM = FoM(T=400) – FoM(T=100)) resulted from lowering the temperature can further be improved by downscaling of Lg and by using low-k gate dielectric.

Design Insights into Thermal Performance of Vertically Stacked JL-NSFET with High-k Gate Dielectric for Sub 5-nm Technology Node

Developing technologies need smaller and faster IC's, hence transistor size has to be scaled down. In order to satisfy this, transistor size in a chip has been decreased drastically from micro range to nano-range. MOSFET was the mass element in any IC at micro size, but when scaled down to nano regime performance degrades because of short channel effects. It is shown here that the FinFET, which gives the better performance and scalability, will replace it. However in 14 nm node and beyond, FinFET also has certain disadvantages; hence some performance enhancement techniques have been introduced to yield good results in 14 nm node. Such techniques include changing the channel materials, use of high-K gate dielectric, etc. We used parameters defined in ITRS update 2013 to simulate FinFET in 14 nm node and we adapted various techniques. Finally the performance enhancement of both finFET and CNTFET for 14 nm node is shown.

Performance enhancement of FINFET and CNTFET at different node technologies

The Delay and Speed plays a complementary role in ICs, as the delay decreases the speed increases and vice-versa. The scaling of MOSFETs has resulted in reduction in size of ICs. As we scale down to nanometer regime, the Short Channel Effects (SCEs) of MOSFET affects the system performance and reliability. Here in this paper we discuss on FinFET, which is an alternate MOSFET, through which the SCEs are reduced. The performance analysis of FinFET based digital applications such as inverter circuit, NAND and NOR gates at 22nm and 14nm technology nodes is also discussed. The simulations are done using HSPICE. The results obtained for delay, average power dissipation and total power dissipation are so promising that FinFET will be an alternative to traditional MOSFET's issues. The noise margin calculation of FinFET based Inverter circuit at 22nm and 14nm is also discussed.

Design and evaluation of FinFET based digital circuits for high speed ICs

In today’s world scenario more than 85-90% of the chip area is mainly occupied by memory. There is a need for faster and reliable memory system for various integrated devices from computers to various handheld devices. The memory devices such as SRAM, DRAM etc. were served by the traditional MOSFETs till to date but as the demand of the better performing and the compact modeling of the integrated devices are causing the failure of MOSFETs operations. The MOSFET scaling is suffered by Short Channel Effects (SCE’s). SRAM is one of the memories mainly used in the cache memory of devices. It must be faster, less power consuming and reliable but this is affected by CMOS scaling causing process variations. Here in this paper the alternate solution to the issues faced by MOSFET based SRAM is overcome by FinFET based SRAM. A 6T short gated FinFET based SRAM is taken for the study and the spice models are created at 22nm and 14nm using Predictive Technology Models (PTM) and simulated using HSPICE. The performance is analyzed in terms of Static Noise Margin (SNM), power and delay for the 6T SRAM. The results shows FinFET based SRAM is faster, reliable and the power consumption is significantly reduced and offers good tradeoffs at lower technology nodes.

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Design and Evaluation of FinFET based SRAM Cells at 22nm and 14nm Node Technologies

The miniaturization of device dimensions has been used to improve the performance of bulk MOSFETSs. The scaling of MOSFET dimensions has led to increased speed, high driving capability, ICs with increased functionality and reduced cost. Further scaling of Devices in the nanometer range has become extremely difficult. FinFET and Nanowire transistors promise to replace traditional MOSFETs because of their superior ability in controlling leakage and minimizing short channel effects while delivering a strong drive current. Here we show detailed performance analysis of MOSFET, FINFET and NANOWIRE devices in terms of parameters like Transconductance, threshold voltage, leakage and Ion/Ioff have been thoroughly carried out with MUGFET simulation tool. The simulation results have revealed that the short channel effects have been minimized and Ion /Ioff ratio and transconductance have been improved with device scaling at different technology nodes.

Performance evaluation of FinFET and Nanowire at different technology nodes

Here we have successfully implemented Voice activated intelligent system for elderly and physically challenged people to make them more self-dependent. This is a major breakthrough in automation technology. The prototype developed using energia tool is capable of controlling electrical devices in a home or office. This is mainly targeted to elderly and disabled people. The system incorporates automatic voice recognition engines. It is demonstrated with practical coverage up to 10 meters. Here our system controls multiple home appliances based on the user voice commands. The response of the proposed system to different voice commands is good compared to other existing systems.

Raju Hajare

Papers

Performance enhancement of FINFET and CNTFET at different node technologies

Design and evaluation of FinFET based digital circuits for high speed ICs

Design and Evaluation of FinFET based SRAM Cells at 22nm and 14nm Node Technologies

Performance evaluation of FinFET and Nanowire at different technology nodes

Design and development of voice activated intelligent system for elderly and physically challenged