Showing papers by "Rakesh Malik published in 2011"
01 Jan 2011
TL;DR: A model is developed to optimize the performance of high speed serial link in terms of jitter and amplitude performance and Taguchi array optimization has been applied during the optimization process.
Abstract: System level signal integrity and power integrity problems for high speed serial links have been explored in this paper. An example of the USB 2.0 IP has been used in this paper, but the analysis is generic for all serial links. This paper considers signal and power integrity as effects simultaneoulsy. A model is developed to optimize the performance of high speed serial link in terms of jitter and amplitude performance. Sensitivity analysis is carried out with a set of dependent parameters affecting the performance. Taguchi array optimization has been applied during the optimization process. Finally, reflection gain concept is also applied to further improve the performance for the eye diagram. A strong correlation between measured and simulated results is shown. A generic methodology for SI and PI for high speed serial links is presented with complete analysis of package, board, termination, squidd card, decoupling network etc. Index Terms—Signal integrity, power integrity, serial links, bit error rate (BER), high speed data transmission
7 citations
14 Mar 2011
TL;DR: HSLINK system is optimized for better SI and PI and linear models for eye amplitude and jitter are derived by Design of Experiments (DOE) and cost effective solution strategy is presented using linear models obtained.
Abstract: Signal Integrity (SI) and Power Integrity (PI) are the most inportant characteristics for system level design, simulation and analysis of high speed systems. In this paper, HSLINK system is optimized for better SI and PI. Linear models for eye amplitude and jitter are derived by Design of Experiments (DOE). Cost effective solution strategy is also presented using linear models obtained.
1 citations