—The US National Institute of Standards and Technology initiated a standardization process for post-quantum cryptography in 2017, with the aim of selecting key encapsulation mechanisms and signature schemes that can withstand the threat from emerging quantum computers. In 2022, Falcon was selected as one of the standard signature schemes, eventually attracting effort to optimize the implementation of Falcon on various hardware architectures for practical applications. Recently, Mitaka was proposed as an alternative to Falcon, allowing parallel execution of most of its operations. These recent advancements motivate us to develop high throughput implementations of Falcon and Mitaka signature schemes on Graphics Processing Units (GPUs), a massively parallel architecture widely available on cloud service platforms. In this paper, we propose the first parallel implementation of Falcon on various GPUs. An iterative version of the sampling process in Falcon, which is also the most time-consuming Falcon operation, was developed. This allows us to implement Falcon signature generation without relying on expensive recursive function calls on GPUs. In addition, we propose a parallel random samples generation approach to accelerate the performance of Mitaka on GPUs. We evaluate our implementation techniques on state-of-the-art GPU architectures (RTX 3080, A100, T4 and V100). Experimental results show that our Falcon-512 implementation achieves 58 , 595 signatures/second and 2 , 721 , 562 verifications/second on an A100 GPU, which is 20 . 03 × and 29 . 51 × faster than the highly optimized AVX2 implementation on CPU. Our Mitaka implementation achieves 161 , 985 signatures/second and 1 , 421 , 046 verifications/second on the same GPU. Due to the adoption of a parallelizable sampling process, Mitaka signature generation enjoys ≈ 2 – 20 × higher throughput than Falcon on various GPUs. The high throughput signature generation and verification achieved by this work can be very useful in various emerging applications

High Throughput Lattice-based Signatures on GPUs: Comparing Falcon and Mitaka

In this paper, an efficient method for analysis of power supply induced jitter (PSIJ) is presented. In the proposed approach, the noise spectrum for an arbitrary noise is generated via Fourier series and the knowledge-based neural network (KBNN) is generated to accurately predict the response of PSIJ transfer function (PSIJTF) using the training data extracted from two types of models, analytical closed-form expressions as well as computationally expensive circuit simulator. Employing KBNN based transfer function model with the noise spectrum gives reasonably accurate estimation of PSIJ for multiple input noises. A case study with 32nm CMOS technology is presented to demonstrate the validity of the proposed model compared to a circuit simulator.

Efficient Estimation of PSIJ via Jitter Transfer Function and Knowledge-based Neural Networks

The concept of Industrial Revolution 4.0 (IR4.0) has attracted a lot of attention from academia and industry in recent years. Many existing manufacturers are forced to relook into their exiting production processes, exploring modern ways to improve the yields. Unfortunately, this is difficult to achieve when the data is limited. The situation is particularly serious for many SMEs in developing countries, wherein the manufacturing machines are not up-to-date and lack computational and connectivity capabilities. As an initiative to tackle this issue, we present an end-to-end Internet-of-Things (IoT) solution in this paper, aiming at tracking the production performance of old manufacturing machines reliably. This paper goes over the designs and reasoning behind the proposed solution. We also demonstrated that with careful optimization, high-performance secure encryption key encapsulation and decapsulation are achievable, which is critical for secure communication in IoT systems. As of the time of writing, our IoT system had been deployed in a real manufacturing environment and had been running continuously for approximately 365 days without data loss over the wide area network (WAN).

A Flexible and Reliable Internet-of-Things Solution for Real-Time Production Tracking With High Performance and Secure Communication

Modern NVIDIA GPU architectures offer dot-product instructions (DP2A and DP4A), with the aim of accelerating machine learning and scientific computing applications. These dot-product instructions allow the computation of multiply-and-add instructions in a single clock cycle, effectively achieving higher throughput compared to conventional 32-bit integer units. In this paper, we show that the dot-product instruction can also be used to accelerate matrix-multiplication and polynomial convolution operations, which are widely used in post-quantum lattice-based cryptographic schemes. In particular, we propose a highly optimized implementation of FrodoKEM wherein the matrix-multiplication is accelerated by the dot-product instruction. We also present specially designed data structures that allow an efficient implementation of Saber key-encapsulation mechanism, utilizing the dot-product instruction to speed-up the polynomial convolution. The proposed FrodoKEM implementation achieves $4.37\times $ higher throughput than the state-of-the-art implementation on a V100 GPU. This paper also presents the first implementation of Saber on GPU platforms, achieving 124,418, 120,463, and 31,658 key exchanges per second on RTX3080, V100, and T4 GPUs, respectively. Since matrix-multiplication and polynomial convolution operations are the most time-consuming operations in lattice-based cryptographic schemes, we strongly believe that the proposed methods can be beneficial to other KEM and signatures schemes based on lattices.

DPCrypto: Acceleration of Post-Quantum Cryptography Using Dot-Product Instructions on GPUs

In this article, a knowledge-based artificial neural network (ANN) is developed for predicting jitter in CMOS inverter circuits in the presence of power supply noise (PSN). The proposed ANN provides for efficient training in a hybrid approach using input data extracted from both analytical closed-form expressions and a circuit simulator. The proposed ANN demonstrates a reasonably accurate prediction of power supply-induced jitter (PSIJ) with results that closely match that from directly using a circuit simulator (HSPICE) for a case study with 22-nm CMOS technology.

Development of Knowledge-Based Artificial Neural Networks for Analysis of PSIJ in CMOS Inverter Circuits

Sparse LU factorization is a key tool in the solution of large linear set of algebraic equations encompassing a wide range of computing applications. Recent advances in this field exploit the massively parallel architecture of the GPUs via left-looking algorithm (LLA) and right-looking algorithm (RLA). In this paper, adaptive cluster mode is proposed to improve the state-of-the-art in LLA for GPU platforms. The proposed method takes into consideration of varying sparsity at different levels during cluster mode execution, to adaptively configure the GPU block size and the number of parallel columns. The new refinements for LLA are also integrated with the dynamic parallelism that is available in modern GPU architectures. The paper also provides a comprehensive performance comparison of the LLA and hybrid RLA along with state-of-the-art advances on the same GPU platform. The results indicate that, when implemented with similar refinements and on a same platform, LLA provides better performance compared to the hybrid-RLA. The results would be useful to the scientific community while making decision on adopting LLA or RLA algorithms for sparse LU factorization.

Algorithmic Advancements and a Comparative Investigation of Left and Right Looking Sparse LU Factorization on GPU Platform for Circuit Simulation

Vector Fitting (VF) is widely used for system identification via rational function approximation from tabulated data of high-speed modules. Since the algorithm is iterative in nature, minimizing its computational cost and parallel efficiency on mixed CPU and GPU environments is critical in reducing the overall time needed for convergence. In this paper, a novel Tensor-core based QR decomposition method is introduced to provide significant speedups to the most computationally expensive steps in the VF process, QR factorization and the solution to a set of linear equations, exploiting the GPU platforms with Tensor Core architectures.

Ramachandra Achar

Papers

DPCrypto: Acceleration of Post-Quantum Cryptography Using Dot-Product Instructions on GPUs

Development of Knowledge-Based Artificial Neural Networks for Analysis of PSIJ in CMOS Inverter Circuits

Efficient Estimation of PSIJ via Jitter Transfer Function and Knowledge-based Neural Networks

Algorithmic Advancements and a Comparative Investigation of Left and Right Looking Sparse LU Factorization on GPU Platform for Circuit Simulation

TC-QR: Tensor Core-based QR Solver for Efficient GPU-based Vector Fitting