Showing papers by "Ranjan Ghosh published in 2016"

An Efficient FPGA Implementation of Optimized Anisotropic Diffusion Filtering of Images

Abstract: Digital image processing is an exciting area of research with a variety of applications including medical, surveillance security systems, defence, and space applications. Noise removal as a preprocessing step helps to improve the performance of the signal processing algorithms, thereby enhancing image quality. Anisotropic diffusion filtering proposed by Perona and Malik can be used as an edge-preserving smoother, removing high-frequency components of images without blurring their edges. In this paper, we present the FPGA implementation of an edge-preserving anisotropic diffusion filter for digital images. The designed architecture completely replaced the convolution operation and implemented the same using simple arithmetic subtraction of the neighboring intensities within a kernel, preceded by multiple operations in parallel within the kernel. To improve the image reconstruction quality, the diffusion coefficient parameter, responsible for controlling the filtering process, has been properly analyzed. Its signal behavior has been studied by subsequently scaling and differentiating the signal. The hardware implementation of the proposed design shows better performance in terms of reconstruction quality and accelerated performance with respect to its software implementation. It also reduces computation, power consumption, and resource utilization with respect to other related works.

NIST Statistical Test Suite

Abstract: The NIST Statistical Test Suite has 15 tests. The principal strategy of the NIST Statistical Test Suite is to judge statistical randomness property of random bit generating algorithms. Based on 300 to 500 different keys, the algorithm generates a series of even number of different long random sequences of n bits, n varying between 13 and 15 lacs, each of which is tested by the 15 tests. Each test has a specific statistic parameter for bit sequences under the assumption of randomness and calculates the deviation of the respective statistic parameter for the series of tested bit sequences.

Accelerating More Secure RC4 : Implementation of Seven FPGA Designs in Stages upto 8 byte per clock.

Abstract: RC4 can be made more secured if an additional RC4-like Post-KSA Random Shuffing (PKRS) process is introduced between KSA and PRGA. It can also be made significantly faster if RC4 bytes are processed in a FPGA embedded system using multiple coprocessors functioning in parallel. The PKRS process is tuned to form as many S-boxes as required by particular design architectures involving multiple coprocessors, each one undertaking byte-by-byte processing. Following a ecent idea [1] [2] the speed of execution of each processor is also enhanced by another fold if the byte-by-byte processing is replaced by a scheme of processing two consecutive bytes together. Adopting some new innovative concepts, three hardware design architectures are proposed in a suitable FPGA embedded system involving 1, 2 and 4 coprocessors functioning in parallel and a study is made on accelerating RC4 by processing bytes in byte-by-byte mode achieving throughputs from 1-byte-in-1-clock to 4-bytes-in-1-clock. The hardware designs are appropriately upgraded to accelerate RC4 further by processing 2 onsecutive RC4 bytes together and it has been possible to achieve a maximum throughput of 8-bytes per clock in Xilinx Virtex-5 LX110t FPGA [3] architecture followed by secured data communication between two FPGA boards.

Study of Randomness in AES Ciphertexts Produced by Randomly Generated S-Boxes and S-Boxes with Various Modulus and Additive Constant Polynomials

Abstract: In Advanced Encryption Standard (AES), the standard S-Box is conventionally generated by using a particular irreducible polynomial {11B} in GF(28) as the modulus and a particular additive constant polynomial {63} in GF(2), though it can be generated by many other polynomials. In this paper, it has been shown that it is possible to generate secured AES S-Boxes by using some other selected modulus and additive polynomials and also can be generated randomly, using a PRNG like BBS. A comparative study has been made on the randomness of corresponding AES ciphertexts generated, using these S-Boxes, by the NIST Test Suite coded for this paper. It has been found that besides using the standard one, other moduli and additive constants are also able to generate equally or better random ciphertexts; the same is true for random S-Boxes also. As these new types of S-Boxes are user-defined, hence unknown, they are able to prevent linear and differential cryptanalysis. Moreover, they act as additional key-inputs to AES, thus increasing the key-space.

Dynamic Ciphering-15 Based on Multiplicative Polynomial Inverses Over Galois Field GF(7 3 )

Abstract: A new stream ciphering technique based on multiplicative polynomial inverses over Galois Field GF(73) is proposed, where a set of randomly generated key-bytes, between 1 and 15, is dynamically permuted and XORed with the identical number of message bytes. The output cipher is tested using NIST Statistical Test Suite and results are compared with that obtained by the well-known RC4 stream cipher. The new cipher is statistically random and observed to be better than RC4.