An efficient and cost-effective power converter is a pre-requisite for the modern power applications. With the evolvement of matured medium power self-commutated switching devices, multilevel inverters (MLIs) are emerged as a promising solution for high-power medium-voltage applications. Though, MLIs are performing a promising role in industrial applications, their high device count, size, cost and control complexities have restricted their market penetration. To address the disadvantages of MLIs, researchers are continuously contributing to new generation topologies under the name of reduced switch count (RSC) MLIs. From the past decade, numerous RSC-MLIs topologies have been reported for various applications. Therefore, this paper presents a comprehensive review and classification of RSC-MLI topologies, in terms of their structure, features, limitations, suitability and selection for specific applications.

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A Survey on Reduced Switch Count Multilevel Inverters

The multilevel inverters (MLI) are resourceful in producing a voltage waveform with superior-quality staircase counterfeit sinusoidal and depressed harmonic distortion (THD). Several conventional topologies are proposed to realize the MLI however, the limitations of these topologies may involve more DC sources and power-switching devices, and less THD, which in turn, increases the cost and size of the inverter. These drawbacks can be eliminated with the proposed hybrid Cascaded H-Bridge Multilevel Inverter with reduced components topology. As compared with the established MLI topologies the recommended topology having a reduced number of DC sources, power-switching devices, component count level factor, lesser TSV, more efficient, lesser THD, and cost-effective. The proposed MLI is a blend of a single-phase T-Type inverter and an H-Bridge module made of sub switches. This article incorporates the design and simulation of the multilevel inverter with staircase PWM technique. Further, the 9-level and 17-level MLI is examined with different combinational loads. The proposed inverter is stable during nonlinear loads, and it is well suited for FACTS and renewable energy grid-connected applications. An operational guideline has been explained with correct figures and tables. The Output voltage wave is realized in numerical simulation. Finally, the experimental demonstrations were performed by implementing a hardware prototype setup for both linear and nonlinear loads using the dSPACE controller laboratory.

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Design and Implementation of Seventeen Level Inverter With Reduced Components

This paper presents a new boost inverter topology with nine level output voltage waveform using a single dc source and two switched capacitors. The capacitor voltages are self-balancing and thus is devoid of any sensors and auxiliary circuitry. The output voltage is twice higher than the input voltage, which eliminates the need for an input dc boost converter especially when the inverter is powered from a renewable source. The merits of the proposed topology in terms of the number of devices and cost are highlighted by comparing the recent and conventional inverter topologies. In addition to this, the total voltage stress of the proposed topology is lower and have a maximum efficiency of 98.25%. The operation and dynamic performance of the proposed topology have been simulated using PLECS software and are validated using an experimental setup considering a different dynamic operation.

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A Single DC Source Nine-Level Switched-Capacitor Boost Inverter Topology With Reduced Switch Count

A new switched-capacitor-based topology with features of boosting and self-voltage balancing of the capacitor has been proposed in this study. The proposed multilevel inverter topology uses two isolated dc voltage sources with a switched-capacitor to produce 11 levels across the load. In this study, two different modes of the selection of dc voltage sources have been discussed for the proposed topology. Furthermore, the generalised structure of the proposed boost topology has also been discussed. Quantitative comparison with several topologies has been carried out to set the benchmark of the proposed topology. Selective harmonic elimination pulse width modulation technique has been adopted to improve the performance of the suggested topology. The power loss analysis of the proposed topology gives the maximum efficiency of 96.5% at the output power of 100 W and has an efficiency value of 95.3% at the output power of 500 W. The proposed topology has been simulated using PLECS and the simulation results have been verifying using an experimental prototype. The proposed topology has been tested for the different types of load and changes in the modulation index. The experimental results have verified the feasibility of the proposed topology.

https://ietresearch.onlinelibrary.wiley.com/doi/pdf/10.1049/iet-pel.2019.0826

Dual input switched-capacitor-based single-phase hybrid boost multilevel inverter topology with reduced number of components

The merit of switched-capacitors-based multilevel inverters (SCMLIs) is generally quantified in terms of a “cost function” (CF) that incorporates parameters such as voltage gain, component count, total standing voltage (TSV), and number of levels. In this article, a 13-level inverter is proposed with the aim of achieving a low value of CF. The proposed single-stage SCMLI uses one input source and three capacitors to attain a voltage gain of 3. It requires 13 power switches, of which the peak inverse voltage (PIV) of nine switches is restricted to the source voltage. The remaining four switches have PIV equal to twice the source voltage and they operate at low frequency. Thus, for all switches, the PIV is less than the amplitude of the output voltage. Moreover, the capacitors are self-balanced at all regions of modulation index values. The proposed inverter is validated through simulation and experimental results. A comparison of the proposed topology with other contemporary SCMLIs shows that it is highly competent in terms of CF, PIV and TSV requirements, waveform resolution, and capability to achieve voltage balancing of capacitors at low values of modulation index.

A Switched-Capacitors-Based 13-Level Inverter

Switched capacitors (SCs)-based modules are being increasingly used for multilevel DC to AC power conversion, especially for low input voltage applications. Many of these topologies operate in two stages involving H-bridge switches, which endure high-voltage stress. The SC 9-level module (SC9LM) presented here operates in a single stage with one DC source and two capacitors. In addition, the peak inverse voltage of all power switches is confined to the voltage of the input DC source. The proposed 9-level module ensures a reduced number of power switches. In addition, with appropriate utilisation of states, two of the eleven switches in the module operate at fundamental switching frequency, thereby minimising the switching losses. A single SC9LM achieves a voltage gain of two. The proposed module is validated through circuit analysis followed by simulation and experimental results.

https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/iet-epa.2019.0053

Switched capacitors 9-level module (SC9LM) with reduced device count for multilevel DC to AC power conversion

Switched capacitors are being increasingly employed in multilevel inverters for various applications. Of the new topologies that have been recently introduced, single-stage switched-capacitor module (S
 3
CM) has gained a lot of attention. In this work, a modified version of S
 3
CM is presented that leads to a significant reduction in a number of power switches, with a simultaneous reduction in total peak inverse voltage. The proposed topology can generate 9 voltage levels in symmetric configuration and 11 voltage levels in asymmetric configuration with two dc sources, two capacitors, and eight power switches. Moreover, for the higher voltage-rated power switches in the structure, the switching losses are minimised by fundamental frequency operation of these switches. The operation and the performance of the proposed topology have been validated through simulation and experimental results of a single-phase prototype with symmetric and asymmetric source configurations.

Reduced device count version of single-stage switched-capacitor module for cascaded multilevel inverters

A major disadvantage of two-stage topologies of switched capacitors based multilevel inverters is the use of H-bridge switches which endure high peak-inverse-voltage (PIV). In such topologies, the H-bridge stage is preceded by a level-generation stage which synthesises unipolar voltage levels. In this work, a bi-polar module is proposed which can synthesise nine levels at the AC terminals with a single DC input. The proposed module uses power switches with PIV equal to that of the input DC source. Use of switched capacitors in each of the proposed module enables a voltage gain of two. Such bi-polar voltage-doubler modules can be easily connected in a cascaded fashion to increase the number of levels, without involving H-bridge switches. Working modes of the module ensure that the capacitors are self-balanced. A complete analysis of the proposed module is presented. Also, experimental results are presented for validation. In addition, a comparison with other topologies has been presented.

https://ietresearch.onlinelibrary.wiley.com/doi/pdf/10.1049/iet-pel.2019.0094

Nine-level voltage-doubler bi-polar module for multilevel DC to AC power conversion

Modularity, efficiency, power quality, and high reliability are the attractive advantages of multilevel inverters (MLIs). But it has limitations in terms of an increased number of semiconductor devices as compared to conventional 2-level inverters. In this paper, a fault-tolerant single-phase 5-level MLI configuration is proposed. The proposed fault-tolerant configuration of the MLI can significantly improve its reliability while maintaining the modularity of its software implementation. Examination, design, and implementing thought for both normal and abnormal operating situations of the proposed MLI are presented in this paper. The feasibility of the proposed fault-tolerant MLI is verified by simulation in MATLAB/Simulink environment and experimental results in a laboratory prototype.

Rekha Agrawal

Papers

Switched capacitors 9-level module (SC9LM) with reduced device count for multilevel DC to AC power conversion

Reduced device count version of single-stage switched-capacitor module for cascaded multilevel inverters

Nine-level voltage-doubler bi-polar module for multilevel DC to AC power conversion

A multilevel inverter structure with open circuit fault-tolerant capability