The impact-induced deposition of Al13 clusters with icosahedral structure on Ni(0 0 1) surface was studied by molecular dynamics (MD) simulation using Finnis–Sinclair potentials. The incident kinetic energy (Ein) ranged from 0.01 to 30 eV per atom. The structural and dynamical properties of Al clusters on Ni surfaces were found to be strongly dependent on the impact energy. At much lower energy, the Al cluster deposited on the surface as a bulk molecule. However, the original icosahedral structure was transformed to the fcc-like one due to the interaction and the structure mismatch between the Al cluster and Ni surface. With increasing the impinging energy, the cluster was deformed severely when it contacted the substrate, and then broken up due to dense collision cascade. The cluster atoms spread on the surface at last. When the impact energy was higher than 11 eV, the defects, such as Al substitutions and Ni ejections, were observed. The simulation indicated that there exists an optimum energy range, which is suitable for Al epitaxial growth in layer by layer. In addition, at higher impinging energy, the atomic exchange between Al and Ni atoms will be favourable to surface alloying.

Nuclear instruments and methods in physics research section B : beam interactions with materials and atoms

Batteries have become fundamental building blocks for the mobility of modern society. Continuous development of novel battery chemistries and electrode materials has nourished progress in building better batteries. Simultaneously, novel device form factors and designs with multi-functional components have been proposed, requiring batteries to not only integrate seamlessly to these devices, but to also be a multi-functional component for a multitude of applications. Thus, in the past decade, along with developments in the component materials, the focus has been shifting more and more towards novel fabrication processes, unconventional configurations, and additional functionalities. This work attempts to critically review the developments with respect to emerging electrochemical energy storage configurations, including, amongst others, paintable, transparent, flexible, wire or cable shaped, ultra-thin and ultra-thick configurations, as well as hybrid energy storage-conversion, or graphene-incorporated batteries and supercapacitors. The performance requirements are elaborated together with the advantages, but also the limitations, with respect to established electrochemical energy storage technologies. Finally, challenges in developing novel materials with tailored properties that would allow such configurations, and in designing easier manufacturing techniques that can be widely adopted are considered.

Design Considerations for Unconventional Electrochemical Energy Storage Architectures

Development of Integrated Optical Circuits depends greatly on progress in coupling light to and between chip devices. Exemplary disclosed embodiments provide a system and method of fabricating couplers for optical chips that may allow for access to devices on the entire chip surface. Cantilever couplers comprising optical waveguides are deflected out-of-plane creating access to remote portions of devices. An exemplary system and method may provide waveguides with tunable angles of deflection creating greater flexibility in optical coupling options.

Cantilever couplers for intra-chip coupling to photonic integrated circuits

Co-integration of sensors with their associated electronics on a single silicon chip may provide many significant benefits regarding performance, reliability, miniaturization and process simplicity without significantly increasing the total cost. Micromachined Thin-Film Sensors for SOI-CMOS Co-integration covers the challenges and interests and demonstrates the successful co-integration of gas-flow sensors on dielectric membrane, with their associated electronics, in CMOS-SOI technology. We firstly investigate the extraction of residual stress in thin layers and in their stacking and the release, in post-processing, of a 1 µm-thick robust and flat dielectric multilayered membrane using Tetramethyl Ammonium Hydroxide (TMAH) silicon micromachining solution. The optimization of its selectivity towards aluminum is largely demonstrated. The second part focuses on sensors design and characteristics. A novel loop-shape polysilicon microheater is designed and built in a CMOS-SOI standard process. High thermal uniformity, low power consumption and high working temperature are confirmed by extensive measurements. The additional gas flow sensing layers are judiciously chosen and implemented. Measurements in the presence of a nitrogen flow and gas reveal fair sensitivity on a large flow velocity range as well as good response to many gases. Finally, MOS transistors suspended on released dielectric membranes are presented and fully characterized as a concluding demonstrator of the co-integration in SOI technology.

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Micromachined thin-film sensors for SOI-CMOS co-integration

The modeling and design of MEMS-scale piezoelectric-based vibration energy harvesters (MPVEH) are presented. The work is motivated by the need for pervasive and limitless power for wireless sensor nodes that have application in structural health monitoring, homeland security, and infrastructure monitoring. A review of prior millito micro-scale harvesters is provided. Common ambient low-level vibration sources are characterized experimentally. Coupled with a dissipative system model and a mechanical damping investigation, a new scale-dependent operating frequency selection scheme is presented. Coupled electromechanical structural models are developed, based on the linear piezoelectric constitutive description, to predict uni-morph and bi-morph cantilever beam harvester performance. Piezoelectric coupling non-intuitively cancels from the power prediction under power-optimal operating conditions, although the voltage and current are still dependent on this property. Piezoelectric material selection and mode of operation ({3-1} vs. {3-3}) therefore have little effect on the maximum power extracted. The model is verified for resonance and off-resonance operation by comparison to new experimental results for a macro-scale harvester. Excellent correlation is obtained away from resonances in the small-strain linear piezoelectric regime. The model consistently underpredicts the response at resonances due to the known non-linear piezoelectric constitutive response (higher strain regime). Applying the model, an optimized single prototype bimorph MPVEH is designed concurrently with a microfabrication scheme. A low-level (2.5 m/s), low-frequency (150 Hz) vibration source is targeted for anti-resonance operation, and a power density of 313 μW/cm and peak-to-peak voltage of 0.38 V are predicted per harvester. Methodologies for the scalar analysis and optimization of uni-morph and bi-morph harvesters are developed, as well as a scheme for chip-level assembly of harvester clusters to meet different node power requirements. Thesis Supervisor: Brian L. Wardle Title: Boeing Assistant Professor

Modeling and design of a MEMS piezoelectric vibration energy harvester

Increased etch rate for implanted oxide with boron, phosphorus, arsenic, and argon is characterized for aqueous and vapor hydrofluoric acid (HF). Destruction by implantation of Si-O bonds makes oxide more reactive to HF. Water being reaction product and catalyst for oxide etching, its amount controls the reaction kinetic. In aqueous solution selectivity of four between implanted and unimplanted oxide is reached but increases up to 200 in vapor HF. In the case of HF etching under vapor phase the generated water increases the etch rate. This technique opens many process possibilities such as etch stop layer development, etching of buried trenches, definition of MEMS anchors, etc. (c) 2006 The Electrochemical Society.

https://iopscience.iop.org/article/10.1149/1.2200307/pdf

Etch Rate Modification of SiO2 by Ion Damage

Boron highly doped silicon is now widely used as etch stop layer in MicroElectroMechanical Systems (MEMS) devices fabrication. The present paper shows the advantages of replacing the p++ Si etch stop layer by a p++ polysilicon layer. The etch rate of Tetramethylammoniunhydroxide (TMAH) is measured for LPCVD polysilicon and silicon doped with Boron at concentrations from 8.1018 up to 4.1020 atoms/cm3 which is the Boron solubility limit into Si. TMAH etch being often used during back-end process, selectivity to aluminium is usually needed. The etch selectivity of various TMAH solutions for p++ Si, p++ Poly and aluminium have been measured, from 25 % to 5 % TMAH pure and mixed with silicon powder and ammonium persulfate. Contrarily to silicon, polysilicon is etched isotropically in TMAH solution which constitutes a great advantage when cavities with vertical walls have to be opened. Although the polysilicon etch rate is higher than the silicon one, the selectivity (doped/undoped) is the same for the both materials, allowing identical uses. Another great advantage of polysilicon is that it can be deposited at any process step and does not require clever epitaxy steps or wafer bonding as for silicon. The surface roughness of the etched Poly region is considerably decreased with TMAH mixed with silicon powder and ammonium persulfate mixture compared to pure 25 % TMAH solution. The definition of buried masks in polysilicon layer through Boron implant is the main foreseen application. The p++ Poly buried mask brings solutions for the fabrication of self-aligned double gate MOS, microfluidic or optical networks in MEMS field.

Advantages of p++ polysilicon etch stop layer versus p++ silicon

The effects of various deposition and annealing conditions of Plasma Enhanced Chemical Vapour Deposited (PECVD) oxide films on residual stress, optical index, BHF etch rate, surface roughness for thick PECVD oxide films are investigated Rapid Thermal Annealing (RTA) and annealing in regular furnaces are both considered and compared AFM measurements were required to measure the oxide surface roughness Thick PECVD oxide films of 15 mu m were deposited on 380 mu m bulk silicon wafer Starting from a conventional recipe the power, the [N/sub 2/O/SiH/sub 4/] ratio and the total gas flow were successively varied An increase of the total gas flow or/and a decrease of power lead to an increase of the BHF etch rate and surface roughness but on the other hand decrease the residual stress A high ratio N/sub 2 /O/SiH/sub 4/ yields to oxide with low BHF etch rate but characterized by higher residual stress RTA reduces the stress and the BHF etch rate drastically and it is more efficient than conventional annealing in standard furnace Actually, RTA reduces stress in a very short period of time (few seconds) compared to standard annealing, and then it does not contribute to doping diffusion of the already implanted regions of the wafer From a compressive stress of about 80 MPa, RTA of 15 s leads to a residual stress of only 30 MPa and bring the BHF etch rate to acceptable values in the range of 2000 A /min for high N /sub 2/O/SiH/sub 4/ ratio oxide One main application of this RTA stress release of oxide is to provide processed wafers with a bow compatible(less than 10 mu m) with Chemical Mechanical Polishing (CMP) or wafer bonding

Stress release of PECVD oxide by RTA

MIMC reliability and electrical behavior defined by a physical layer property of the dielectric

Ion implantation is the mostly used method for semiconductor doping but can also be of interest to change locally the etch rate of silicon and silicon dioxide. Indeed damages induced by ion implantation can increase the etch rate of silicon dioxide by a factor of 200 when etched in vapor HF. Doping species of n or p type increases drastically the etching rate of silicon in HNA. Substitutional boron implanted in silicon can reduce the etch rate of silicon in TMAH from a factor of 200. Etch rate modification by ion implantation can be of interest for the fabrication of buried mask, sacrificial layers and etch stop layers.

Rémy Charavel

Papers

Etch Rate Modification of SiO2 by Ion Damage

Advantages of p++ polysilicon etch stop layer versus p++ silicon

Stress release of PECVD oxide by RTA

MIMC reliability and electrical behavior defined by a physical layer property of the dielectric

Tuning of etching rate by implantation: silicon, polysilicon and oxide