Defect and Fault Tolerance in VLSI Systems

Software-Based Self-Test is an effective methodology for devising the online testing of Systems-on-Chip. In the automotive field, a set of test programs to be run during mission mode is also called Core Self-Test library. This paper introduces many new contributions: (1) it illustrates the several issues that need to be taken into account when generating test programs for on-line execution; (2) it proposed an overall development flow based on ordered generation of test programs that is minimizing the computational efforts; (3) it is providing guidelines for allowing the coexistence of the Core Self-Test library with the mission application while guaranteeing execution robustness. The proposed methodology has been experimented on a large industrial case study. The coverage level reached after one year of team work is over 87 percent of stuck-at fault coverage, and execution time is compliant with the ISO26262 specification. Experimental results suggest that alternative approaches may request excessive evaluation time thus making the generation flow unfeasible for large designs.

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Development Flow for On-Line Core Self-Test of Automotive Microcontrollers

Deep Learning, and in particular its implementation using Convolutional Neural Networks (CNNs), is currently one of the most intensively and widely used predictive models for safety-critical applications like autonomous driving assistance on pedestrian, objects and structures recognition. Today, ensuring the reliability of these innovations is becoming very important since they involve human lives. One of the peculiarities of the CNNs is the inherent resilience to errors due to the iterative nature of the learning process. In this work we present a method-ology to evaluate the impact of permanent faults affecting CNN exploited for automotive applications. Such a characterization is performed through a fault injection enviroment built upon on the darknet open source DNN framework. Results are shown about fault injection campaigns where permanent faults are affecting the connection weights in the LeNet and Yolo; the behavior of the corrupted CNN is classified according to the criticality of the introduced deviation.

A Reliability Analysis of a Deep Neural Network

Software-based self-test (SBST) techniques are used to test processors and processor cores against permanent faults introduced by the manufacturing process or to perform in-field test in safety-critical applications. However, the generation of an SBST program is usually associated with high costs as it requires significant manual effort of a skilled engineer with in-depth knowledge about the processor under test. In this paper, we propose an approach for the automatic generation of SBST programs. First, we detail an automatic test pattern generation (ATPG) framework for the generation of functional test sequences. Second, we describe the extension of this framework with the concept of a validity checker module (VCM), which allows the specification of constraints with regard to the generated sequences. Third, we use the VCM to express typical constraints that exist when SBST is adopted for in-field test. In our experimental results, we evaluate the proposed approach with a microprocessor without interlocked pipeline stages (MIPS)-like microprocessor. The results show that the proposed method is the first approach able to automatically generate SBST programs for both end-of-manufacturing and in-field test whose fault efficiency is superior to those produced by state-of-the-art manual approaches.

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A Flexible Framework for the Automatic Generation of SBST Programs

The saturation of the IJTAG concept and its approval as the IEEE 1687 standard in 2014 has generated a wave of research activities and created demand for a set of appropriate and challenging benchmarks. This paper presents such a set developed by an industrial and academic consortium and constructed in a way that facilitates objective comparison of experimental results across research groups as well as represents challenging network examples exhaustively utilizing features and constructs defined by the standard. The suite is arranged in four comprehensive categories, each having its particular purpose and composition principles, as described in the paper. We have also made an analysis of limitations of previous popular and ad-hoc benchmark sets as these limitations majorly motivated our current action. The new public-domain benchmarks are distributed together with source files and documentation through the dedicated web site. Some of the previous research results on IEEE 1687 have been reapplied on the new benchmarks set, thus creating an important initial reference point for the research community.

A suite of IEEE 1687 benchmark networks

Due to the increasing usage of embedded instruments in many electronic devices, new solutions to effectively access these instruments appeared, including the new IEEE 1687 standard. The approach supported by IEEE 1687 allows a flexible access to embedded instruments through the Boundary Scan interface. The IEEE 1687 network includes a set of reconfigurable scan chains. This paper addresses the issue of testing the circuitry implementing them, checking whether any permanent hardware fault exists, affecting either the registers associated to the instruments made accessible by the network, or the configuration structures it embeds (e.g., the multiplexers and the associated flip-flops). The paper proposes an approach, in which the IEEE 1687 network undergoes a sequence of test sessions, each composed of a configuration phase and a test phase. By properly selecting the network configurations to be used, we can guarantee that the method can test any permanent fault possibly affecting the network. We also provide some experimental results gathered on a set of benchmark networks, allowing to practically evaluate the viability of the approach.

On the testability of IEEE 1687 networks

The paper is dealing with the in-field test of the decode unit of RIS C processors through functional test programs following the SBST approach. The paper details a strategy based on instruction classification and manipulation, and signatures collection. The method does not require the knowledge of detailed implementation information (e.g., the netlist), but is based on the Instruction Set of the processor. The proposed method is evaluated on an industrial SoC device, which includes a PowerPC derived processor. Results demonstrate the efficiency and effectiveness of the strategy; the proposed solution reaches over 90% of stuck-at fault coverage while an instruction coverage based approach does not overcome 70%.

Riccardo Cantoro

Papers

Development Flow for On-Line Core Self-Test of Automotive Microcontrollers

A Flexible Framework for the Automatic Generation of SBST Programs

A suite of IEEE 1687 benchmark networks

On the testability of IEEE 1687 networks

On the in-field functional testing of decode units in pipelined RISC processors