R
Richard Conlin
Researcher at Tilera
Publications - 3
Citations - 791
Richard Conlin is an academic researcher from Tilera. The author has contributed to research in topics: Row & Column (database). The author has an hindex of 2, co-authored 3 publications receiving 771 citations.
Papers
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Proceedings ArticleDOI
TILE64 - Processor: A 64-Core SoC with Mesh Interconnect
Shane L. Bell,Bruce S. Edwards,John Amann,Richard Conlin,Kevin Joyce,V. Leung,J. MacKay,M. Reif,Liewei Bao,J.F. Brown,Matthew Mattina,Chyi-Chang Miao,Carl Ramey,David Wentzlaff,W. Anderson,E. Berger,N. Fairbanks,D. Khan,F. Montenegro,J. Stickney,J. Zook +20 more
TL;DR: The TILE64TM processor is a multicore SoC targeting the high-performance demands of a wide range of embedded applications across networking and digital multimedia applications.
Patent
Computing in parallel processing environments
Patrick Robert Griffin,Mathew Hostetter,Anant Agarwal,Chyi-Chang Miao,Christopher D. Metcalf,Bruce Edwards,Carl Ramey,Rosenbluth Mark B,David Wentzlaff,Christopher J. Jackson,Ben Harrison,Kenneth Steele,John Amann,Shane L. Bell,Richard Conlin,Kevin Joyce,Christine Deignan,Liewei Bao,Matthew Mattina,Ian Rudolf Bratt,Richard Schooler +20 more
TL;DR: In this article, a processor is coupled to a communication network among the cores, and a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores.
Patent
Method and system for routing scan chains in an array of processor resources
TL;DR: In this paper, a method and system for routing a group of scan chains to the group of processor resources in a semiconductor chip is presented. But this method requires a test-pattern generator to generate test signals and send the test signals to the processor resources.