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Anant Agarwal
Researcher at Massachusetts Institute of Technology
Publications - 250
Citations - 17595
Anant Agarwal is an academic researcher from Massachusetts Institute of Technology. The author has contributed to research in topics: Cache & Shared memory. The author has an hindex of 64, co-authored 248 publications receiving 17306 citations. Previous affiliations of Anant Agarwal include Stanford University & Tilera.
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Journal ArticleDOI
The Raw microprocessor: a computational fabric for software circuits and general-purpose programs
Michael Taylor,Jung Hun Kim,Jason Miller,David Wentzlaff,Fae Ghodrat,Ben Greenwald,Henry Hoffman,Paul Johnson,Jae-Wook Lee,Woo Sik Lee,A. Ma,Arvind Saraf,M. Seneski,Nathan Shnidman,Volker Strumpen,Matthew I. Frank,Saman Amarasinghe,Anant Agarwal +17 more
TL;DR: The Raw microprocessor research prototype uses a scalable instruction set architecture to attack the emerging wire-delay problem by providing a parallel, software interface to the gate, wire and pin resources of the chip.
Journal ArticleDOI
On-Chip Interconnection Architecture of the Tile Processor
David Wentzlaff,Patrick Robert Griffin,Henry Hoffmann,Liewei Bao,Bruce S. Edwards,Carl Ramey,Matthew Mattina,Chyi-Chang Miao,J.F. Brown,Anant Agarwal +9 more
TL;DR: IMesh, the tile processor architecture's on-chip interconnection network, connects the multicore processor's tiles with five 2D mesh networks, each specialized for a different use, taking advantage of the C-based ILIB interconnection library.
Journal ArticleDOI
Baring it all to software: Raw machines
E. Waingold,Michael Taylor,Devabhaktuni Srikrishna,Vivek Sarkar,Whay S. Lee,Victor W. Lee,Jason Kim,Matthew I. Frank,P. Finch,Rajeev Barua,Jonathan Babb,Saman Amarasinghe,Anant Agarwal +12 more
TL;DR: The most radical of the architectures that appear in this issue are Raw processors-highly parallel architectures with hundreds of very simple processors coupled to a small portion of the on-chip memory, allowing synthesis of complex operations directly in configured hardware.
Proceedings ArticleDOI
DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling
Chen Sun,Chia-Hsin Owen Chen,George Kurian,Lan Wei,Jason Miller,Anant Agarwal,Li-Shiuan Peh,Vladimir Stojanovic +7 more
TL;DR: DSENT, a NoC modeling tool for rapid design space exploration of electrical and opto-electrical networks, is presented and the results show the implications of different technology scenarios and the need to reduce laser and thermal tuning power in a photonic network due to their non-data-dependent nature.
Proceedings ArticleDOI
An evaluation of directory schemes for cache coherence
TL;DR: In this article, the cache coherence in shared-memory multiprocessors has been addressed using two basic approaches: directory schemes and snoopy cache schemes, which have been given less attention in the past several years.