The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies.
Table of contents

1 Introduction to Analog Design
2 Basic MOS Device Physics
3 Single-Stage Amplifiers
4 Differential Amplifiers
5 Passive and Active Current Mirrors
6 Frequency Response of Amplifiers
7 Noise
8 Feedback
9 Operational Amplifiers
10 Stability and Frequency Compensation
11 Bandgap References
12 Introduction to Switched-Capacitor Circuits
13 Nonlinearity and Mismatch
14 Oscillators
15 Phase-Locked Loops
16 Short-Channel Effects and Device Models
17 CMOS Processing Technology
18 Layout and Packaging

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Design of Analog CMOS Integrated Circuits

The Fifth Edition of this academically rigorous text provides a comprehensive treatment of analog integrated circuit analysis and design starting from the basics and through current industrial practices. The authors combine bipolar, CMOS and BiCMOS analog integrated-circuit design into a unified treatment that stresses their commonalities and highlights their differences. The comprehensive coverage of the material will provide the student with valuable insights into the relative strengths and weaknesses of these important technologies.

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Analysis and Design of Analog Integrated Circuits

Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

/pdf/fundamentals-of-modern-vlsi-devices-471xd7l9pf.pdf

Fundamentals of Modern VLSI Devices

A general model is introduced which is capable of making accurate, quantitative predictions about the phase noise of different types of electrical oscillators by acknowledging the true periodically time-varying nature of all oscillators. This new approach also elucidates several previously unknown design criteria for reducing close-in phase noise by identifying the mechanisms by which intrinsic device noise and external noise sources contribute to the total phase noise. In particular, it explains the details of how 1/f noise in a device upconverts into close-in phase noise and identifies methods to suppress this upconversion. The theory also naturally accommodates cyclostationary noise sources, leading to additional important design insights. The model reduces to previously available phase noise models as special cases. Excellent agreement among theory, simulations, and measurements is observed.

/pdf/a-general-theory-of-phase-noise-in-electrical-oscillators-a928ervz6d.pdf

A general theory of phase noise in electrical oscillators

We describe a distributed position-based network protocol optimized for minimum energy consumption in mobile wireless networks that support peer-to-peer communications. Given any number of randomly deployed nodes over an area, we illustrate that a simple local optimization scheme executed at each node guarantees strong connectivity of the entire network and attains the global minimum energy solution for stationary networks. Due to its localized nature, this protocol proves to be self-reconfiguring and stays close to the minimum energy solution when applied to mobile networks. Simulation results are used to verify the performance of the protocol.

Minimum energy mobile wireless networks

A class AB downconversion mixer for 2.4 GHz wireless LAN applications is presented. The circuit is implemented in a 13 GHz f/sub T/ BiCMOS process, and consumes 7.9 mA total current from a 3 V supply. A single-balanced design using bond-wire degeneration in the common-emitter driver stage is optimal for power consumption and noise figure. The design has a power gain of 4.5 dB, a single-side band noise figure of 10 dB, an input third-order intercept point of 1 dBm, and an input 1 dB compression point of -7.5 dBm.

A 2.4 GHz monolithic mixer for wireless LAN applications

The signal performance of transistor mixers at high frequencies is investigated by treating the basic nonlinear differential equations of the transistor. These equations have been solved in normalised form on a digital computer, and the results have been obtained as normalised graphs, which allow rapid prediction of the conversion transconductance at higher frequencies. Transistor parameters and operating conditions for maximum conversion gain at high frequencies are readily determined from these results. The transistor-mixer input impedance is also investigated in detail, and it is shown, in general, to be higher than the corresponding amplifier input impedance. Although calculable, the precise input impedance cannot be predicted as simply as the conversion transconductance.

https://ieeexplore.ieee.org/iel5/5247218/5249458/05250212.pdf

Signal processes in transistor mixer circuits at high frequencies

In a phase-locked loop comprising a phase detector (1), a loop filter (5) and a controlled oscillator (17) which are arranged on a common integrated circuit, interferences coupled into the substrate of the integrated circuit by other parts of the circuit are suppressed. In a first embodiment of the invention, this object is achieved in that the controlled oscillator (17) is preceded by a capacitive voltage divider (9) which comprises at least two capacitances (10, 12), the controlled oscillator (17) is controlled in dependence upon the output signal of the capacitive voltage divider (9), and the capacitive voltage divider (9), together with the phase detector (1), the loop filter (5) and the controlled oscillator (17) is arranged on an integrated circuit. In accordance with a second embodiment of the invention, the reduction of interference is achieved in that the controlled oscillator (17) has a differential structure and comprises at least two voltage-controlled current sources (18, 19) whose circuits are coupled to a power supply potential and to a substrate on which the integrated circuit is arranged, the controlled oscillator (17) has an output stage (20) which is arranged behind the voltage-controlled current sources (18, 19) and generates two differential digital signals in dependence upon the differential signals applied thereto, which differential digital signals are generated with a high edge steepness by means of switching between two potentials and are applied to amplifier stages (56, 57) which are arranged between power supply potential and reference potential and supply two differential output signals operating at reference potential.

Phase-locked loop with capacitive voltage divider for reducing jitter

This work presents a novel method for efficiently analyzing the relationship between spectral regrowth and physical distortion mechanisms in radio frequency power amplifiers. It utilizes a Volterra series model whose coefficients are computed from basic SPICE parameters. The analysis uses a decomposition of the Volterra kernels into simpler subsystems in order to greatly reduce the computation times. The method is applied to the design of several bipolar-transistor power amplifiers after a series-based model is developed for representing the increase in active device forward transit time at high collector current densities. A number of single-stage SiGe power amplifiers have been designed, fabricated, and tested using the IEEE 802.11b and IS-95 modulation schemes at different carrier frequencies, and these results are compared with the theoretical analysis.

Analysis and simulation of spectral regrowth in radio frequency power amplifiers

Circuit design techniques for realizing wideband, low-noise, matched-impedance amplifiers in submicrometer MOS technology are discussed. A circuit configuration with two feedback loops has been fabricated in an experimental 1-/spl mu/m NMOS technology. The fabricated amplifier has an insertion gain of 16.35 dB, a -3-dB bandwidth of 758 MHz, a maximum input voltage standing-wave ratio (VSWR) of 2.45, a maximum output VSWR of 1.60, and an average noise figure of 6.7 dB (with reference to a 50-/spl mu/m source resistance) from 10 to 758 MHz.

Robert G. Meyer

Papers

A 2.4 GHz monolithic mixer for wireless LAN applications

Signal processes in transistor mixer circuits at high frequencies

Phase-locked loop with capacitive voltage divider for reducing jitter

Analysis and simulation of spectral regrowth in radio frequency power amplifiers

Wide-band, low-noise, matched-impedance amplifiers in submicrometer MOS technology