Showing papers by "Robert Henderson published in 2003"

SXGA pinned photodiode CMOS image sensor in 0.35 /spl mu/m technology

Abstract: A 30 frames/s SXGA 5.6 /spl mu/m pinned photodiode pixel column parallel CMOS image sensor achieves 340 /spl mu/V noise floor and 40 pA/cm/sup 2/ dark current. Performance is limited by pixel 1/f noise, not by the ADC noise floor of 140 /spl mu/V. The column ADC memory employs a custom DRAM to save area. The sensor utilizes a 0.35 /spl mu/m 1P 3M CMOS process.

Image sensor reading during reset and reading on release from reset

Abstract: A solid state image sensor has an array of pixels in which each column has a reset voltage line and a read line. The sensor is reset and read a row at a time, with reset-related values held in a frame buffer for subsequent subtraction from read values. Reset-related values are derived in each column by sampling the voltage during reset on one capacitor and the voltage on release of reset on a second capacitor, and differencing these values to provide an output for the frame buffer. This provides a reduction in the size of frame buffer which would otherwise be required.

A CMOS image sensor with a double-junction active pixel

Abstract: A CMOS image sensor that employs a vertically integrated double-junction photodiode structure is presented. This allows color imaging with only two filters. The sensor uses a 184*154 (near-QCIF) 6-transistor pixel array at a 9.6-/spl mu/m pitch implemented in 0.35-/spl mu/m technology. Results of the device characterization are presented. The imaging performance of an integrated two-filter color sensor is also projected, using measurements and software processing of subsampled images from the monochrome sensor with two color filters.

Image sensor with readout circuit

Abstract: An image sensor has an array of pixels. Each column has a first and a second column line connected to a read-reset amplifier/comparator which acts in a first mode as a unity gain buffer amplifier to reset the pixels via the first lines, and in a second mode acts as a comparator and AD converter to produce digitized reset and signal values. The reset and signal values are read out a line at a time in interleaved fashion. Reset values are stored in a memory and subsequently subtracted from the corresponding signal values. The arrangement reduces both fixed pattern and kT/C noise.

Image sensor with capacitive amplifier and associated methods

Abstract: An image sensor includes pixels which are of the four-transistor, PIN photodiode type. In each pixel, the charge on a photodiode is transferred by a transfer gate to a sensing node. Readout of reset and read voltages is via an amplifier. A gain capacitor is connected in feedback across the amplifier. Read and reset gates are controlled so that the pixel is reset to a virtual ground voltage controlled by the gain capacitor. This is independent of the pixel parasitic capacitance.

Method for down-scaling a digital image and a digital camera for processing images of different resolutions

Abstract: A digital camera for capturing and processing images of different resolutions and a corresponding method for down-scaling a digital image are provided. The method includes forming an image of a real scene on an image sensor that is made up of a plurality of pixels arranged in a matrix. The method further includes addressing and reading pixels in the matrix to obtain analog quantities related to the pixels luminance values, converting the analog quantities from the pixels matrix into digital values, and processing the digital values to obtain a data file representing the image of the real scene. To reduce computation time and power consumption, the addressing and reading of the pixels includes selecting a group of pixels from the matrix, and storing the analog quantities related to the pixels of the selected group of pixels into an analog storing circuit. The stored analog quantities are averaged to obtain an analog quantity corresponding to an average pixel luminance value.

Improvements in or relating to CMOS Image sensors

Abstract: An active pixel array has the signal output of each pixel (10) connected to a first column conductor (16) and a reset switch connected to a second column conductor (20). The column conductors (16,20) are connected to a read-reset amplifier (22) which can be configured to operate in a first mode in which a reset voltage is applied to the second column line (20), and a second mode in which pixel output signals are buffered from the first column line (16). The read-reset amplifier (22) can also operate as a comparator forming part of an ADC circuit.

Active-pixel image sensors

Abstract: An image sensor has an array of pixels read by column circuits to provide reset and read samples on a pair of sample capacitors To alleviate the effects of parasitic capacitance in the region of the sample capacitors, a modified timing arrangement is used Both sample switches are operated simultaneously to pre-charge both sample capacitors with a pixel signal value One sample switch is operated after reset to apply a reset value to one of the pre-charged sample capacitors

Reset function for image sensor

Abstract: A solid state image sensor has an array of pixels (10) in which each column has a reset voltage line (VRT) and a read line (Vx). The sensor is reset and read a row at a time, with reset-related values held in a frame store for subsequent subtraction from read values. Reset-related values are derived in each column by sampling the voltage during reset on one capacitor (14) and the voltage on release of reset on a second capacitor (12), and differencing these values (16) to provide an output for the frame store. This gives a reduction in the size of frame store which would otherwise be required.