The impact of urban air pollution on the environments and human health has drawn increasing concerns from researchers, policymakers and citizens. To reduce the negative health impact, it is of great importance to measure the air pollution at high spatial resolution in a timely manner. Traditionally, air pollution is measured using dedicated instruments at fixed monitoring stations, which are placed sparsely in urban areas. With the development of low-cost micro-scale sensing technology in the last decade, portable sensing devices installed on mobile campaigns have been increasingly used for air pollution monitoring, especially for traffic-related pollution monitoring. In the past, some reviews have been done about air pollution exposure models using monitoring data obtained from fixed stations, but no review about mobile sensing for air pollution has been undertaken. This article is a comprehensive review of the recent development in air pollution monitoring, including both the pollution data acquisition and the pollution assessment methods. Unlike the existing reviews on air pollution assessment, this paper not only introduces the models that researchers applied on the data collected from stationary stations, but also presents the efforts of applying these models on the mobile sensing data and discusses the future research of fusing the stationary and mobile sensing data.

https://www.mdpi.com/2220-9964/6/12/389/pdf

A review of urban air pollution monitoring and exposure assessment methods

A 4 GHz third-order continuous-time ΔΣ ADC is presented with a loop filter topology that absorbs the pole caused by the input capacitance of its 4-bit quantizer and also compensates for the excess delay caused by the quantizer's latency. The ADC was implemented in 45 nm-LP CMOS and achieves 70 dB DR and -74 dBFS THD in a 125 MHz BW, while dissipating 260 mW from 1.1/1.8 V supply. The ADC occupies 0.9 mm2 including the modulator, clock circuitry and decimation filter.

/pdf/a-4-ghz-continuous-time-delta-sigma-adc-with-70-db-dr-and-74-39339ypdcu.pdf

A 4 GHz Continuous-Time $\Delta\Sigma$ ADC With 70 dB DR and $-$ 74 dBFS THD in 125 MHz BW

This paper presents a third order, single-loop, continuous-time ΔΣ modulator with an internal 4-bit quantizer. The modulator is sampled at 500 MHz, and features an oversampling ratio of only 10. Therefore, DAC linearization by dynamic element matching is ineffective, and the DAC nonlinearities are not corrected within the ΔΣ modulator loop but in the subsequent digital circuit. The unit element mismatches are digitally estimated based on a correlation, and correction factors are thus derived. Moreover, in order to achieve a low-power operation, all amplifiers are compensated for finite gain-bandwidth related non-idealities. In the presented work, this compensation includes the fast proportional loop, which is used to compensate for excess loop delay. The presented ΔΣ modulator has been realized in a 1.2 V, 90 nm CMOS process and achieves an SNDR of 63.5 dB and an SFDR of 81 dB within a 25 MHz bandwidth. The modulator occupies an active die area of only 0.15 mm2 and has a power consumption of 8 mW, with an additional 0.02 mm2 and 0.42 mW estimated for the digital DAC correction logic. The overall modulator achieves a figure of merit of 138 fJ/conv.

An 8.5 mW Continuous-Time $\Delta \Sigma $ Modulator With 25 MHz Bandwidth Using Digital Background DAC Linearization to Achieve 63.5 dB SNDR and 81 dB SFDR

This paper presents a pixel pitch-matched readout chip for 3-D photoacoustic (PA) imaging, featuring a dedicated signal conditioning and delta-sigma modulation integrated within a pixel area of 250 $\mu \text{m}$ by 250 $\mu \text{m}$ . The proof-of-concept receiver was implemented in an STMicroelectronics’s 28-nm Fully Depleted Silicon On Insulator technology, and interfaces to a $4 \times 4$ subarray of capacitive micromachined ultrasound transducers (CMUTs). The front-end signal conditioning in each pixel employs a coarse/fine gain tuning architecture to fulfill the 90-dB dynamic range requirement of the application. The employed delta-sigma beamforming architecture obviates the need for area-consuming Nyquist ADCs and thereby enables an efficient in-pixel A/D conversion. The per-pixel switched-capacitor $\Delta \Sigma $ modulator leverages slewing-dominated and area-optimized inverter-based amplifiers. It occupies only 1/4th of the pixel, and its area compares favorably with state-of-the-art designs that offer the same SNR and bandwidth. The modulator’s measured peak signal-to-noise-and-distortion ratio is 59.9 dB for a 10-MHz input bandwidth, and it consumes 6.65 mW from a 1-V supply. The overall subarray beamforming approach improves the area per channel by 7.4 times and the single-channel SNR by 8 dB compared to prior art with similar delay resolution and power dissipation. The functionality of the designed chip was evaluated within a PA imaging experiment, employing a flip-chip bonded 2-D CMUT array.

A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI

A current-steering digital-to-analog converter (DAC) was fabricated using a 90 nm CMOS technology. Its dynamic performance is enhanced by adopting a digital random return-to-zero (DRRZ) operation and a compact current cell design. The DRRZ also facilitates a current-cell background calibration technique that ensures the DAC static linearity. The measured differential nonlinearity (DNL) is 0.5 LSB and the integral nonlinearity (INL) is 1.2 LSB. At 1.25 GS/s sampling rate, the DAC achieves a spurious-free dynamic range (SFDR) better than 70 dB up to 500 MHz input frequency. The DAC occupies an active area of 1100 750 . It consumes a total of 128 mW from a 1.2 V and a 2.5 V supply.

https://ir.nctu.edu.tw:443/bitstream/11536/14920/1/000297573300010.pdf

A 12-Bit 1.25-GS/s DAC in 90 nm CMOS With $ > $ 70 dB SFDR up to 500 MHz

This paper presents the first dynamic zoom ADC. Intended for audio applications, it achieves 109-dB DR, 106-dB signal-to-noise ratio, and 103-dB SNDR in a 20-kHz bandwidth, while dissipating only 1.12 mW. This translates into the state-of-the-art energy efficiency as expressed by a Schreier FoM of 181.5 dB. It also achieves the state-of-the-art area efficiency, occupying only 0.16 mm2 in the 0.16- $\mu \text{m}$ CMOS. These advances are enabled by the use of concurrent fine and coarse conversions, dynamic error-correction techniques, and a dynamically biased inverter-based operational transconductance amplifier.

/pdf/a-dynamic-zoom-adc-with-109-db-dr-for-audio-applications-30vti1auo0.pdf

A Dynamic Zoom ADC With 109-dB DR for Audio Applications

This article presents a continuous-time zoom analog to digital converter (ADC) for audio applications. It employs a high-speed asynchronous SAR ADC that dynamically updates the references of a continuous-time delta–sigma modulator (CTDSM). Compared to previous switched-capacitor (SC) zoom ADCs, its input impedance is essentially resistive, which relaxes the power dissipation of its reference and input buffers. Fabricated in a 160-nm CMOS process, the ADC occupies 0.27 mm2 and achieves 108.1-dB peak SNR, 106.4-dB peak signal to noise and distortion ratio (SNDR), and 108.5-dB dynamic range in a 20-kHz bandwidth while consuming 618 $\mu \text{W}$ . This results in a Schreier figure of merit (FoM) of 183.6 dB.

/pdf/a-continuous-time-zoom-adc-for-low-power-audio-applications-47d4wgt9th.pdf

A Continuous-Time Zoom ADC for Low-Power Audio Applications

This paper presents a dynamic zoom analog-to-digital converter for use in low-bandwidth ( $\Delta \Sigma$ ADC. Compared to previous zoom ADCs, faster reference updates relax the loop filter requirements, thus allowing the adoption of energy-efficient amplifiers. Fabricated in a 0.16- $\mu \text{m}$ CMOS process, the prototype occupies 0.26 mm2 and achieves 119.1-dB peak signal-to-noise ratio (SNR), 118.1-dB peak signal-to-noise-and-distortion-ratio (SNDR), and 120.3-dB dynamic range (DR) in a 1-kHz bandwidth while consuming 280 $\mu \text{W}$ . This results in a Schreier figure of merit (FoM) of 185.8 dB.

/pdf/a-280-mu-w-dynamic-zoom-adc-with-120-db-dr-and-118-db-sndr-2s36wgvliq.pdf

A 280 $\mu$ W Dynamic Zoom ADC With 120 dB DR and 118 dB SNDR in 1 kHz BW

Audio codecs for automotive applications and smartphones require up to five stereo channels to achieve effective acoustic noise and echo cancellation, thus demanding ADCs with low power and minimal die area. Zoom-ADCs should be well suited for such applications, since they combine compact and energy-efficient SAR ADCs with low-distortion ΔΣ ADCs to simultaneously achieve high energy efficiency, small die area, and high linearity [1,2]. However, previous implementations were limited to the conversion of quasi-static signals, since the two ADCs were operated sequentially, with a coarse SAR conversion followed by, a much slower, fine ΔΣ conversion. This work describes a zoom-ADC with a 20kHz bandwidth, which achieves 107.5dB DR and 104.4dB SNR while dissipating 1.65mW and occupying 0.16mm2. A comparison with recent state-of-the-art ADCs with similar resolution and bandwidth [3–7] shows that the ADC achieves significantly improved energy and area efficiency. These advances are enabled by the use of concurrent fine and coarse conversions, dynamic error-correction techniques, and an inverter-based OTA.

15.7 A 1.65mW 0.16mm2 dynamic zoom-ADC with 107.5dB DR in 20kHz BW

This paper reports a readout circuit for a resistive CO2 sensor, which operates by measuring the CO2-dependent thermal conductivity of air. A suspended hot-wire transducer, which acts both as a resistive heater and temperature sensor, exhibits a CO2-dependent heat loss to the surrounding air, allowing CO2 concentration to be derived from its temperature rise and power dissipation. The circuit employs a dual-mode incremental delta-sigma ADC to digitize these parameters relative to those of an identical, but isolated, reference transducer. This ratiometric approach results in a measurement that does not require precision voltage or power references. The readout circuit uses dynamically-swapped transducer pairs to cancel their baseline-resistance, so as to relax the required dynamic range of the ADC. In addition, dynamic element matching (DEM) is used to bias the transducer pairs at an accurate current ratio, making the measurement insensitive to the precise value of the bias current. The readout circuit has been implemented in a standard 0.16 $\mu \text {m}$ CMOS technology. With commercial resistive micro-heaters, a CO2 sensing resolution of about 200 ppm ( $1\sigma $ ) was achieved in a measurement time of 30 s. Similar results were obtained with CMOS-compatible tungsten-wire transducers, paving the way for fully-integrated CO2 sensors for air-quality monitoring.

/pdf/a-ratiometric-readout-circuit-for-thermal-conductivity-based-493aa2tidv.pdf

Robert van Veldhoven

Papers

A Dynamic Zoom ADC With 109-dB DR for Audio Applications

A Continuous-Time Zoom ADC for Low-Power Audio Applications

A 280 $\mu$ W Dynamic Zoom ADC With 120 dB DR and 118 dB SNDR in 1 kHz BW

15.7 A 1.65mW 0.16mm2 dynamic zoom-ADC with 107.5dB DR in 20kHz BW

A Ratiometric Readout Circuit for Thermal-Conductivity-Based Resistive CO 2 Sensors