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Robin Cerutti
Researcher at STMicroelectronics
Publications - 28
Citations - 619
Robin Cerutti is an academic researcher from STMicroelectronics. The author has contributed to research in topics: MOSFET & Transistor. The author has an hindex of 10, co-authored 28 publications receiving 609 citations. Previous affiliations of Robin Cerutti include Philips.
Papers
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Proceedings ArticleDOI
Poly-gate replacement through contact hole (PRETCH): a new method for high-k/metal gate and multi-oxide implementation on chip
S. Harrison,Philippe Coronel,Antoine Cros,Robin Cerutti,Francois Leverd,A. Beverina,Romain Wacquez,J. Bustos,D. Delille,B. Tavel,D. Barge,J. Bienacel,M.-P. Samson,F. Martin,S. Maitrejean,Daniela Munteanu,J.L. Autran,Thomas Skotnicki +17 more
TL;DR: In this paper, the poly-gate replacement through contact hole (PRETCH) concept enables replacement of initial poly-silicon gate and/or gate oxide by any gate stack desired.
Proceedings ArticleDOI
Unexpected mobility degradation for very short devices : A new challenge for CMOS scaling
Antoine Cros,K. Romanjek,D. Fleury,S. Harrison,Robin Cerutti,Philippe Coronel,B. Dumont,A. Pouydebasque,Romain Wacquez,Blandine Duriez,Romain Gwoziecki,Frederic Boeuf,H. Brut,Gerard Ghibaudo,Thomas Skotnicki +14 more
TL;DR: In this article, the role of non-Coulombian defects, which can be healed by increasing the annealing temperature, is evidenced, and a new mobility degradation specific to short channel MOSFETs is studied and elucidated.
Journal ArticleDOI
Quantum Short-channel Compact Modelling of Drain-Current in Double-Gate MOSFET
TL;DR: In this article, a continuous compact model for the drain current, including short-channel effects and carrier quantization in Double-Gate MOSFETs, is developed, particularly well-adapted to ultra-scaled devices, with short channel lengths and ultra-thin silicon films.
Patent
Conductive lines buried in insulating areas
TL;DR: An integrated circuit comprising a semiconductor substrate in which active areas surround or are surrounded by hollowings filled with an insulator, and in which a conductive region is embedded in the insulator of at least one hollowing, the conductive regions being connected to a reference voltage and being connected at least a neighboring element of the circuit is defined in this paper.
Proceedings ArticleDOI
Highly performant double gate MOSFET realized with SON process
S. Harrison,Philippe Coronel,Francois Leverd,Robin Cerutti,R. Palla,D. Delille,S. Borel,S. Jullian,Roland Pantel,S. Descombes,Didier Dutartre,Yves Morand,M.-P. Samson,Damien Lenoble,Alexandre Talbot,Alexandre Villaret,Stephane Monfray,Pascale Mazoyer,J. Bustos,H. Brut,Antoine Cros,Daniela Munteanu,Jean-Luc Autran,Thomas Skotnicki +23 more
TL;DR: In this article, highly performant double gate devices have been obtained with very high Ion/Ioff trade off drive currents of 1954 /spl mu/A/A//spl m/m (Ioff = 283 nA/m) and 1333 /spl µ/A+m/m µ/m m/a+spl m /m) at 12 V with Tox = 20 /spl Aring/ and Lgate = 70 nm.