According to an embodiment, a sample-hold circuit according to this embodiment is made up of a first device having a first withstand voltage and a second device having a second withstand voltage lower than the first withstand voltage. The sample-hold circuit includes a first switch element, a first capacitor, a second switch element, a third switch element, and a fourth switch element. The first switch element has the first withstand voltage. The first switch element operates upon receiving a first signal output from the device having the first withstand voltage. The second switch element has the first withstand voltage. The third switch element has the second withstand voltage. The fourth switch element has the second withstand voltage.

Sample-hold circuit and AD converter

The device comprises a bipolar transistor with emitter, base, collector, base-collector junction and base-emitter junction, a collector-to-base breakdown voltage, a quenching component electrically connected with the base or the collector, and a switching circuitry configured to apply a forward bias to the base-emitter junction The bipolar transistor is configured for operation at a reverse collector-to-base voltage above the breakdown voltage

Light emitting semiconductor device for generation of short light pulses

A current integrator includes an operational amplifier, an integration capacitor and an offset cancelation capacitor. The operational amplifier includes a first input stage and a second input stage. The first input stage is coupled to an input terminal of the current integrator. The integration capacitor is coupled between the first input stage of the operational amplifier and an output terminal of the current integrator. The offset cancelation capacitor is coupled to the second input stage of the operational amplifier.

Current integrator and related signal processing system

A circuit arrangement comprises a first branch (101) comprising a resistor of variable resistance (131) and a diode-connected bipolar transistor (134) and a second branch comprising a resistor of fixed resistance (141) and another diode-connected bipolar transistor (135). A control loop (110) reproduces a voltage drop at the resistor of variable resistance (131) to a voltage drop at the resistor of fixed resistance (141). Output terminals (136, 137) are connected to the bipolar transistors (134, 135) to supply a differential voltage (VBE1, VBE2). The circuit arrangement may be used as an analog frontend circuit in a gas sensor or a temperature sensor arrangement.

Circuit arrangement and sensor arrangements including the same

A sensing circuit for sensing an analog signal includes a level shifter that shifts the analog signal from a high voltage domain to a low voltage domain. The signal originates from the high voltage domain, and is passed to the low voltage domain through the level shifter. A source line provides the analog signal, which can be selectively switched into a sense amplifier circuit. The sense amplifier is in the low voltage domain and generates a digital output to represent the sensed analog signal.

Low voltage, low power sensing based on level shifting sensing circuit

An analog-to-digital converter (10) comprises a first and a second sampling capacitor (24, 25), a first integrator (26), a first and a second input switch (31, 32) coupling a first input terminal (11) and a common mode terminal (39) to a first electrode of the first sampling capacitor (24), a third and a fourth input switch (33, 34) coupling a second input terminal (12) and the common mode terminal (39) to a first electrode of the second sampling capacitor (25), a fifth and a sixth input switch (35, 36) coupling a second electrode of the first sampling capacitor (24) to an amplifier common mode terminal (40) and the first integrator input (27), and a seventh and an eighth input switch (37, 38) coupling a second electrode of the second sampling capacitor (25) to the amplifier common mode terminal (40) and the second integrator input (28).

Analog-to-digital converter, measurement arrangement and method for analog-to-digital conversion

A measurement circuitry (MC) for evaluating a resistance of a resistive gas sensor (GS) comprises a first current path (P1), wherein a first logarithmic compression circuit (LC1) is arranged in the first current path (P1). A reference resistor (Rreference) and a second logarithmic compression circuit (LC2) is arranged in a second current path (P2) of the measurement circuitry (MC). A voltage generator (VG) provides a fixed voltage excitation for the resistive gas sensor (GS) and the reference resistor (Rreference). A first current (I1) received from the resistive gas sensor (GS) flows from the gas sensor (GS) via the first current path (P1) into the first logarithmic compression circuit (LC1). An evaluation circuit (EC) determines the resistance (Rs) of the resistive gas sensor (GS) in dependence on a first and second output signal (Ve1, Ve2) of the first and the second logarithmic compression circuit (LC1, LC2).

Measurement circuitry for evaluating a resistance of a resistive gas sensor

An electric circuit arrangement for galvanic isolated communication comprises a transmitter circuit (120) having an input side (E120) for applying a digital signal (PWM) and an output side (A120) for generating an output signal (AS) in dependence on the digital signal (PWM). The circuit arrangement further comprises a receiver circuit (220) having an input side (E220) for receiving an input signal (ES) and having an output side (A220) for generating a reconstructed digital signal (PWM') in dependence on the input signal (ES), and a transformer (210) for inductive coupling the output side (A120) of the transmitter circuit (120) to the input side (E220) of the receiver circuit (220).

Electric circuit arrangement for galvanic isolated communication

This paper proposes a switched-capacitor amplifier capable of generating a constant output voltage in both the phases of the clock, even in the presence of op-amp offset. Thus it has the advantage that the subsequent A/D stage can operate with at least double the data rate. The architecture is implemented in AMS 0.35um CMOS process and operates on a supply of 5V.

Rohit Ranganathan

Papers

Analog-to-digital converter, measurement arrangement and method for analog-to-digital conversion

Measurement circuitry for evaluating a resistance of a resistive gas sensor

Electric circuit arrangement for galvanic isolated communication

Pseudo-Continuous Output Switched-Capacitor Amplifier for Rail-to-Rail Current Sensing Application