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A survey of optimization techniques for thermal-aware 3D processors

NoC routing protocols – objective-based classification

3D ICs can take advantage of a scalable communication platform, commonly referred to as the Networks-on-Chip (NoC). In the basic form of 3D-NoC, all routers are vertically connected. Partially connected 3D-NoC has emerged because of physical limitations of using vertical links. Routing is of great importance in such partially connected architectures. A high-performance, fault-tolerant and adaptive routing strategy with respect to the communication flow among the cores is crucial while freedom from livelock and deadlock has to be guaranteed. In this paper we introduce a new routing algorithm for partially connected 3D-NoCs. The routing algorithm is adaptive and tolerates the faults on vertical links as compared to the predesigned routing algorithms. Our results show a $40-50\%$ improvement in the fraction of intact inter-level communications when the fault tolerant algorithm is used. This routing algorithm is light-weight and has only one virtual channel along the $Y$ dimension.

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A Resilient Routing Algorithm with Formal Reliability Analysis for Partially Connected 3D-NoCs

Freedom from deadlock is one of the most important issues when designing routing algorithms in on-chip/off-chip networks. Many works have been developed upon Dally's theory proving that a network is deadlock-free if there is no cyclic dependency on the channel dependency graph. However, finding such acyclic graph has been very challenging, which limits Dally's theory to networks with a low number of channels. In this paper, we introduce three theorems that directly lead to routing algorithms with an acyclic channel dependency graph. We also propose the partitioning methodology, enabling a design to reach the maximum adaptiveness for the n-dimensional mesh and k-ary n-cube topologies with any given number of channels. In addition, deadlock-free routing algorithms can be derived ranging from maximally fully adaptive routing down to deterministic routing. The proposed theorems can drastically remove the difficulties of designing deadlock-free routing algorithms.

/pdf/ebda-a-new-theory-on-design-and-verification-of-deadlock-2vxieytxvd.pdf

EbDa: A New Theory on Design and Verification of Deadlock-free Interconnection Networks

2D-NoCs have been the mainstream approach used to interconnect multi-core systems. 3D-NoCs have emerged to compensate for deficiencies of 2D-NoCs such as long latency and power overhead. A low-latency routing algorithm for 3D-NoC is designed to accommodate high-speed communication between cores. Both simulation and analytical models are applied to estimate the communication latency of NoCs. Generally, simulations are time-consuming and slow down the design process. Analytical models provide, within a fraction of the time, nearly accurate results which can be used by simulation to fine-tune the design. In this paper, a high performance and adaptive routing algorithm has been proposed for partially connected 3D-NoCs. Latency of the routing algorithm under different traffic patterns, different number of elevators and different elevator assignment mechanisms are reported. An analytical model, tailored to the adaptivity of the algorithm and under low traffic scenarios, has been developed and the results have been verified by simulation. According to the results, simulation and analytical results are consistent within a 10 percent margin.

/pdf/lead-an-adaptive-3d-noc-routing-algorithm-with-queuing-59wzbocxfm.pdf

LEAD: An Adaptive 3D-NoC Routing Algorithm with Queuing-Theory Based Analytical Verification

This paper presents an analysis of the effects and propagations of different faults such as Single Event Transient (SET), Multiple Event Transients (MET), Single Event Upset (SEU) and Multiple Bit Upsets (MBU) by simulation-based fault injection into Areoflex Gaisler LEON3 processor which is a 32 bit synthesizable processor based on SPARC V8 architecture. LEON3 is designed for ground-based applications. This investigation is done by injecting nearly 11200 transient faults into different components of LEON3 including flip-flops, registers, register-file and cache memories. The behavior of LEON3 processor against injected faults is reported. Besides, it is shown that nearly 52.83% of SEUs are overwritten, 31.74% of SEUs are latent and finally 15.43% of them are reported as failure while 44.74% of MBUs are overwritten, 38.42% of them are latent and 16.84 of these kind of faults are failed. Also, 98.03% of SETs are overwritten, 0.6% of them are latent and 1.36% of SETs are reported as failures. Finally, the effects of METs are as follows: 96.71% for overwritten faults, 1.15% for latent and 2.14% for failure. Moreover, integer unit and multiplier unit are the most susceptible components against single and multiple faults respectively.

Susceptibility Analysis of LEON3 Embedded Processor against Multiple Event Transients and Upsets

3D-NoC has emerged to provide fast and power efficient connection between the layers of 2D-NoCs using Through-Silicon-Vias (TSV) Thermal stress, warpage, impurities and misalignment during the manufacturing process make these expensive TSVs vulnerable to faults Chips with faulty TSVs should be either discarded or utilized by providing a proper fault-tolerant method In this paper, we target designing a reconfigurable fault-tolerant routing algorithm capable of tolerating fabrication-time or run-time TSV failures The proposed algorithm ensures a fault-free communication between any two nodes in the presence of TSV failures Experimental results show that the proposed fault-tolerant routing algorithm provides 100% reliability as long as there is one healthy TSV in the eastmost or westmost column The reliability of the counterpart algorithm, the Elevator-first routing algorithm, drops to 75% and 45% in presence of one and two faulty TSVs, respectively

/pdf/cobra-low-cost-compensation-of-tsv-failures-in-3d-noc-mh76rpy8e7.pdf

CoBRA: Low cost compensation of TSV failures in 3D-NoC

The cost and reliability issues of TSVs move 3D-NoCs toward heterogonous designs with limited number of TSVs. However, designing a deadlock-free routing algorithm for such heterogonous architectures is extremely challenging due to the increased possibilities of forming cycles between and within layers for 3D designs. In this paper, we target designing a routing algorithm for heterogeneous 3D-NoCs with the capability of working under the technical limit in which there is just one TSV in the network. This algorithm is light-weight and provides adaptivity by using only one virtual channel along the Y dimension.

Ronak Salamat

Papers

A Resilient Routing Algorithm with Formal Reliability Analysis for Partially Connected 3D-NoCs

LEAD: An Adaptive 3D-NoC Routing Algorithm with Queuing-Theory Based Analytical Verification

Susceptibility Analysis of LEON3 Embedded Processor against Multiple Event Transients and Upsets

CoBRA: Low cost compensation of TSV failures in 3D-NoC

An Adaptive, Low Restrictive and Fault Resilient Routing Algorithm for 3D Network-on-Chip