N
Nader Bagherzadeh
Researcher at University of California, Irvine
Publications - 333
Citations - 6083
Nader Bagherzadeh is an academic researcher from University of California, Irvine. The author has contributed to research in topics: Scheduling (computing) & Network on a chip. The author has an hindex of 34, co-authored 329 publications receiving 5489 citations. Previous affiliations of Nader Bagherzadeh include University of California & Apple Inc..
Papers
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Journal ArticleDOI
MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications
TL;DR: The MorphoSys architecture is described, including the reconfigurable processor array, the control processor, and data and configuration memories, and the suitability of MorphoSy for the target application domain is illustrated with examples such as video compression, data encryption and target recognition.
Journal ArticleDOI
Design and Implementation of the MorphoSys Reconfigurable ComputingProcessor
Ming-Hau Lee,H. Singh,Guangming Lu,Nader Bagherzadeh,Fadi J. Kurdahi,Eliseu M. Chaves Filho,Vladimir Alves +6 more
TL;DR: The results indicate that the MorphoSys system can achieve significantly better performance for most of these applications in comparison with other systems and processors.
Journal ArticleDOI
Novel Robust Single Layer Wire Crossing Approach for Exclusive OR Sum of Products Logic Design with Quantum-Dot Cellular Automata
Proceedings ArticleDOI
A Wireless Network-on-Chip Design for Multicore Platforms
TL;DR: An on-chip communication infrastructure based on a network-on-chip architecture and a hybrid mechanism to transfer data among IP cores by taking advantages of both wired and wireless communications are developed.
Proceedings ArticleDOI
Power-aware scheduling under timing constraints for mission-critical embedded systems
TL;DR: A new scheduling technique for supporting the design and evaluation of a class of power-aware systems in mission-critical applications that satisfies stringent min/max timing and max power constraints and makes the best effort to satisfy the min power constraint.