The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies.
Table of contents

1 Introduction to Analog Design
2 Basic MOS Device Physics
3 Single-Stage Amplifiers
4 Differential Amplifiers
5 Passive and Active Current Mirrors
6 Frequency Response of Amplifiers
7 Noise
8 Feedback
9 Operational Amplifiers
10 Stability and Frequency Compensation
11 Bandgap References
12 Introduction to Switched-Capacitor Circuits
13 Nonlinearity and Mismatch
14 Oscillators
15 Phase-Locked Loops
16 Short-Channel Effects and Device Models
17 CMOS Processing Technology
18 Layout and Packaging

/pdf/design-of-analog-cmos-integrated-circuits-35wxhwa3a6.pdf

Design of Analog CMOS Integrated Circuits

This paper presents a two-stage, compact, power-efficient 3 V CMOS operational amplifier with rail-to-rail input and output ranges. Because of its small die area of 0.04 mm/sup 2/, it is very suitable as a VLSI library cell. The floating class-AB control is shifted into the summing circuit, which results in a noise and offset of the amplifier which are comparable to that of a three stage amplifier. A floating current source biases the combined summing circuit and the class-AB control. This current source has the same structure as the class-AB control which provides a power-supply-independent quiescent current. Using the compact architecture, a 2.6 MHz amplifier with Miller compensation and a 6.4 MHz amplifier with cascoded-Miller compensation have been realized. The opamps have, respectively, a bandwidth-to-supply-power ratio of 4 MHz/mW and 11 MHz/mW for a capacitive load of 10 pF. >

/pdf/a-compact-power-efficient-3-v-cmos-rail-to-rail-input-output-4hdavv27ht.pdf

A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries

This paper presents a low-dropout regulator (LDO) for portable applications with an impedance-attenuated buffer for driving the pass device. Dynamically-biased shunt feedback is proposed in the buffer to lower its output resistance such that the pole at the gate of the pass device is pushed to high frequencies without dissipating large quiescent current. By employing the current-buffer compensation, only a single pole is realized within the regulation loop unity-gain bandwidth and over 65deg phase margin is achieved under the full range of the load current in the LDO. The LDO thus achieves stability without using any low-frequency zero. The maximum output-voltage variation can be minimized during load transients even if a small output capacitor is used. The LDO with the proposed impedance-attenuated buffer has been implemented in a 0.35-mum twin-well CMOS process. The proposed LDO dissipates 20-muA quiescent current at no-load condition and is able to deliver up to 200-mA load current. With a 1-muF output capacitor, the maximum transient output-voltage variation is within 3% of the output voltage with load step changes of 200 mA/100 ns.

/pdf/a-transient-enhanced-low-quiescent-current-low-dropout-119enznkif.pdf

A Transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer Impedance Attenuation

Compact low-voltage power-efficient operational amplifiers are described that are very suitable as very-large-scale-integration library cells because of the small die area of 0.08 mm/sup 2/ and the minimum supply voltage of 1.8 V. A key part of the circuit is the rail-to-rail class-AB output stage with folded mesh feedback control that combines power efficiency with operation down to 1.8 V and allows sufficient gain in a compact two-stage topology. A version with rail-to-rail input stage features a rail-to-rail input range for supply voltages down to 2.5 V. The dc gain of the op amps is more than 80 db while driving 10 k/spl Omega/, and the unity-gain frequency is 4 MHz with phase margin of 67/spl deg/ while driving 5 pF. The equivalent input noise voltage is 38 nV//spl radic/(Hz) at a frequency of 100 kHz. The amplifiers have been implemented in a standard digital 1.6-/spl mu/m complementary metal-oxide-semiconductor process.

/pdf/compact-low-voltage-power-efficient-operational-amplifier-1j3d449uef.pdf

Compact low-voltage power-efficient operational amplifier cells for VLSI

A multistage operational transconductance amplifier with a feedforward compensation scheme which does not use Miller capacitors is introduced. The compensation scheme uses the positive phase shift of left-half-plane (LHP) zeroes caused by the feedforward path to cancel the negative phase shift of poles to achieve a good phase margin. A two-stage path increases further the low frequency gain while a feedforward single-stage amplifier makes the circuit faster. The amplifier bandwidth is not compromised by the absence of the traditional pole-splitting effect of Miller compensation, resulting in a high-gain wideband amplifier. The capacitors of a capacitive amplifier using the proposed techniques can be varied more than a decade without significant settling time degradation. Experimental results for a prototype fabricated in an AMI 0.5-/spl mu/m CMOS process show DC gain of around 90 dB and a 1% settling time of 15 ns for a load capacitor of 12 pF. The power supply used is /spl plusmn/1.25 V.

A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors

Traditionally, CMOS operational amplifiers apply cascoding techniques to ensure an acceptable gain with a minimal number of gain stages. The use of cascode transistors, however, limits the lowest supply voltage of a CMOS op amp. Lowering the threshold voltage of the MOS process, a development already initiated by many VLSI processing facilities, does not lead to a lower minimum supply voltage of the cascode circuits. On the contrary, below a certain threshold voltage the cascode circuits cease to operate. This effect, that renders an important class of op amp circuits useless in the near future, is caused by the independence of the saturation voltage V/sub Daat/ of a MOS device from the threshold voltage V/sub th/. The proposed solution for compensation is the hybrid nested Miller compensation (HNMC) structure or multipath hybrid nested Miller compensation (MHNMC) structure. These structures are discussed and adopted in op amps realized in a standard V/sub th/=0.6 V CMOS process. >

/pdf/a-programmable-1-5-v-cmos-class-ab-operational-amplifier-3i81tsit37.pdf

A programmable 1.5 V CMOS class-AB operational amplifier with hybrid nested Miller compensation for 120 dB gain and 6 MHz UGF

The paper presents a Multipath Miller Zero Cancellation (MMZC) technique to remove the Right Half Plane Zero (RHPZ) in Miller compensated operational amplifiers. For comparison four different CMOS amplifiers have been integrated: a reference circuit without RHPZ removal, two circuits with traditional resistor and cascode removal techniques and finally the circuit with Multipath Miller Zero Cancellation Measurements confirm that MMZC increases the bandwidth of a microamp Miller compensated output stage from 3MHz to 3MHz, while maintaining the robustness necessary for class-AB operation. The traditional methods for RHPZ removal fail under the same conditions and give rise to peaking ('the output bump')

An Operational Amplifier with Multipath Miller Zero Cancellation for RHP Zero Removal

Amplifiers operating under low-voltage and low-power conditions are strongly limited in dynamic range and bandwidth. The maximum dynamic range is limited by the supply power and the thermal noise power in resistors. To obtain the maximum, input and output stages should be able to process signals from rail to rail. Several rail-to-rail input stages and rail-to-rail output stages biased in current-efficient class-AB mode are presented. Also, the bandwidth is limited by the low-power constraint. To reach the maximum bandwidth at sufficient DC gain, the effectivity of several frequency compensation structures is compared, such as Parallel, Miller, and Nested Miller Compensation. Finally, it is shown that the Multipath Nested Miller Compensation combines a very high bandwidth with high gain, while being insensitive to process parameters.

Ruud G. H. Eschauzier

Papers

A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries

A programmable 1.5 V CMOS class-AB operational amplifier with hybrid nested Miller compensation for 120 dB gain and 6 MHz UGF

An Operational Amplifier with Multipath Miller Zero Cancellation for RHP Zero Removal

Low-voltage low-power opamp based amplifiers