In this paper we compare Fully-Depleted SOI (FDSOI) devices with different BOX (Buried Oxide) thicknesses with or without ground plane (GP). With a simple high-k/metal gate structure, the 32 nm devices exhibits Ion/Ioff performances well suited for low power (LP) applications. The different BOX thicknesses and ground plane conditions are compared with bulk 45 nm technology in terms of variability and noise. A 0.499 μm2 SRAM cell has been characterized with less than 50 pA of standby current/cell and a SNM of 210 mV @ Vdd 1 V.

FDSOI devices with thin BOX and ground plane integration for 32 nm node and below

Variation in transistor characteristics is increasing as CMOS transistors are scaled to nanometer feature sizes. This increase in transistor variability poses a serious challenge to the cost-effective utilization of scaled technologies. Meeting this challenge requires comprehensive and efficient approaches for variability characterization, minimization, and mitigation. This paper describes an efficient infrastructure for characterizing the various types of variation in transistor characteristics. A sample of results obtained from applying this infrastructure to a number of technologies at the 90-, 65-, and 45-nm nodes is presented. This paper then illustrates the impact of the observed variability on SRAM, analog and digital circuit blocks used in system-on-chip designs. Different approaches for minimizing transistor variation and mitigating its impact on product performance and yield are also described.

Variation in Transistor Performance and Leakage in Nanometer-Scale Technologies

We present a study of the temperature dependence of transistor mismatch in a 65-nm CMOS platform over a temperature range of 0degC to 125degC. We show that the relative-drain-current-mismatch fluctuation properties improve marginally in strong inversion, while they are strongly affected in the subthreshold region. This is compared and explained with a commonly used model. Furthermore, we analyze the change over temperature of the ION mismatch of individual matched pairs. This analysis shows, for the first time, that although relative-current-mismatch fluctuation standard deviations estimated on whole populations are reduced at higher temperatures, the current mismatch of individual pairs can change substantially over temperature.

The Temperature Dependence of Mismatch in Deep-Submicrometer Bulk MOSFETs

This paper presents a device matching study of a commercial 40-nm bulk CMOS technology operated at cryogenic temperatures. Transistor pairs and linear arrays, optimized for device matching, were characterized over the temperature range from 300 K down to 4.2 K. The device parameters relevant for mismatch, i.e., the threshold voltage and the current factor, were extracted, from which the change in both absolute value and variability as a function of temperature and device size were investigated. It is shown that the Pelgrom scaling law is valid also at 4.2 K and that the simplified Croon model is able to accurately predict drain-current mismatch from moderate to strong inversion over the entire temperature range. Additionally, the characterization of linear device arrays shows exacerbated edge-effects at extremely low temperatures, thus requiring the addition of dummy devices at the array boundary. The result of this study is the first model capable of predicting mismatch over a wide range of operating regions and temperatures.

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Characterization and Modeling of Mismatch in Cryo-CMOS

This paper aims at reviewing the results that we have obtained during the last ten years in the characterization and modeling of transistor mismatch in advanced complementary metal-oxide-semiconductor (CMOS) technologies. First, we review the theoretical background and modeling approaches that are generally employed for analyzing and interpreting the mismatch results. Next, we present the experimental procedures and methodologies that we used for characterizing the transistor matching. Then, we discuss typical matching results that were obtained on modern CMOS technologies and analyze the main variability (mismatch) sources. Finally, we conclude by summarizing our findings and giving some recommendations for future technologies.

Characterization and Modeling of Transistor Variability in Advanced CMOS Technologies

For the first time, a huge drain current fluctuations degradation is shown on heavily pocket-implanted above-micrometer devices. This degradation, which is a serious concern for analog design, is attributed to the high potential barriers that stand at end sides of long devices and mainly control the device electrostatics. Because the barriers height is modulated by the gate voltage, it is demonstrated that the excess fluctuations are highly gate-bias-dependent. The classical drain current model has been shown to be inadequate to describe the current flow through the entire range of applied gate bias voltages. A new adapted model allows for a correct description of the drain current and associated fluctuations.

Abnormally high local electrical fluctuations in heavily pocket-implanted bulk long MOSFET

An improved methodology for the characterization of matching parameters in MOSFETs and bipolar transistors is presented. Because of their statistical nature, only estimation of matching parameters can be provided from given measurements. Considering general /spl sigma//sub /spl Delta/p/ = A/sub p/ / /spl radic/(WL) transistor matching model, the aim of this paper is to discuss, for the first time, the most relevant matching parameter A/sub p/ estimation accuracy. Dispersion on A/sub p/ estimation when using conventional least squares regression on /spl sigma//sub /spl Delta/p/ vs. 1//spl radic/(WL) plots is analytically characterized. Then it is shown that replacing the conventional least squares regression by a weighted least squares regression leads to increased accuracy on A/sub p/ estimation and consequently allows a better detection of physical effects responsible for mismatch.

Improved methodology for better accuracy on transistors matching characterization

Delivering mismatch data that reflect design reality is a real challenge. Indeed, from test structures to final data utilization, many steps can be the source of distortion. The first possible source of distortion is linked to the differences in terms of environment and spacing that might exist between test structure transistors and circuit transistors. The second potential source of distortion is related to the measurements and extraction that can both add extra mismatch. Finally, the data treatment and utilization can constitute other error sources. In this paper, thanks to results from various test structures and device types, the main sources of distortion are pointed out in order to help to set up a reliable chain from matching test structures to matching data utilization.

From MOSFET Matching Test Structures to Matching Data Utilization: Not an Ordinary Task

Many test structures embedded in various technologies were measured to study the spacing impact on MOSFET mismatch. This impact is showed to highly depend on technology, device family, device type and bias conditions. The study of spatial correlation allows to properly model spacing impact on mismatch: this analysis -in this paper focused on MOSFETs- may be extended to any device. Finally, a worst case model that only requires standard matched pairs at minimum spacing is proposed to provide designers the maximum matching degradation that may affect spaced devices.

Spacing impact on MOSFET mismatch

MOS transistor threshold voltage matching is usually modeled proportionally to reverse square root of gate area. Yet this model is not satisfactory when discontinuities are observed. In this paper, a continuous matching model with only two parameters is given. It is obtained by analyzing impact of short channel effects on matching degradation.

S. Bordez

Papers

Abnormally high local electrical fluctuations in heavily pocket-implanted bulk long MOSFET

Improved methodology for better accuracy on transistors matching characterization

From MOSFET Matching Test Structures to Matching Data Utilization: Not an Ordinary Task

Spacing impact on MOSFET mismatch

A Continuous Model for MOSFET VT Matching Considering Additional Length Effects